HYB18T512400B2C datasheet(22/69 Pages) QIMONDA

22 / 69 page

Internet Data Sheet

Rev. 1.12, 2007-05

10062006-YPTZ-CDR7

HY[B/I]18T512[40/80/16]0B2[C/F](L)

512-Mbit Double-Data-Rate-Two SDRAM

TABLE 13

EMRS(2) Programming Extended Mode Register Definition (BA[2:0]=010B)

Field

Bits

Type1)

Description

BA2

Bank Address

Note: BA2 is not available on 256 Mbit and 512 Mbit components

BA2 Bank Address

[15:14]

Bank Adress

00B BA MRS

01B BA EMRS(1)

10B BA EMRS(2)

11B BA EMRS(3): Reserved

A[13:8]

Address Bus

Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration

000000B A Address bits

SRF

Address Bus, High Temperature Self Refresh Rate for

CASE > 85°C

A7 disable

A7 enable 2)

[6:4]

Address Bus

000B A Address bits

DCC

Address Bus, Duty Cycle Correction (DCC)

A3 DCC disabled

A3 DCC enabled

Partial Self Refresh for 4 banks

PASR [2:0]

Address Bus, Partial Array Self Refresh for 4 Banks3)

Note: Only for 256 Mbit and 512 Mbit components

000B PASR0 Full Array

001B PASR1 Half Array (BA[1:0]=00, 01)

010B PASR2 Quarter Array (BA[1:0]=00)

011B PASR3 Not defined

100B PASR4 3/4 array (BA[1:0]=01, 10, 11)

101B PASR5 Half array (BA[1:0]=10, 11)

110B PASR6 Quarter array (BA[1:0]=11)

111B PASR7 Not defined

HYB18T512400B2C Scheda tecnica(PDF) 22 Page - Qimonda AG

HYB18T512400B2C Scheda tecnica(HTML) 22 Page - Qimonda AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

Scheda tecnica Scarica

Link URL