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HYB18T512400B2C Scheda tecnica(PDF) 17 Page - Qimonda AG

Il numero della parte HYB18T512400B2C
Spiegazioni elettronici  512-Mbit Double-Data-Rate-Two SDRAM
PDF  69 Pages
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Produttore elettronici  QIMONDA [Qimonda AG]
Homepage  http://www.qimonda.com
Logo QIMONDA - Qimonda AG

HYB18T512400B2C Scheda tecnica(HTML) 17 Page - Qimonda AG

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Internet Data Sheet
Rev. 1.12, 2007-05
17
10062006-YPTZ-CDR7
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
FIGURE 3
Chip Configuration for
×16 components, PG-TFBGA-84 (top view)
Notes
1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is
data strobe for DQ[7:0]
2. LDM is the data mask signal for DQ[7:0], UDM is the data
mask signal for DQ[15:8]
3.
V
DDL and VSSDL are power and ground for the DLL. VDDL is
connected to
V
DD on the device. VDD, VDDQ, VSSDL, VSS,
and
V
SSQ are isolated on the device.



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