HYB18T512400B2C datasheet(30/69 Pages) QIMONDA

30 / 69 page

Internet Data Sheet

Rev. 1.12, 2007-05

10062006-YPTZ-CDR7

HY[B/I]18T512[40/80/16]0B2[C/F](L)

512-Mbit Double-Data-Rate-Two SDRAM

5.3

DC & AC Characteristics

DDR2 SDRAM pin timing are specified for either single ended

or differential mode depending on the setting of the EMRS(1)

“Enable DQS” mode bit; timing advantages of differential

mode are realized in system design. The method by which the

DDR2 SDRAM pin timing are measured is mode dependent.

In single ended mode, timing relationships are measured

relative to the rising or falling edges of DQS crossing at

REF.

In differential mode, these timing relationships are measured

relative to the crosspoint of DQS and its complement, DQS.

This distinction in timing methods is verified by design and

characterization but not subject to production test. In single

ended mode, the DQS (and RDQS) signals are internally

disabled and don’t care.

TABLE 25

DC & AC Logic Input Levels for DDR2-667 and DDR2-800

TABLE 26

DC & AC Logic Input Levels for DDR2-533 and DDR2-400

Symbol

Parameter

DDR2-667, DDR2-800

Units

Min.

Max.

IH(dc)

DC input logic high

REF + 0.125

DDQ + 0.3

IL(dc)

DC input low

–0.3

REF – 0.125

IH(ac)

AC input logic high

REF + 0.200

—

IL(ac)

AC input low

—

REF – 0.200

Symbol

Parameter

DDR2-533, DDR2-400

Units

Min.

Max.

IH(dc)

DC input logic high

REF + 0.125

DDQ + 0.3

IL(dc)

DC input low

–0.3

REF - 0.125

IH(ac)

AC input logic high

REF + 0.250

—

IL(ac)

AC input low

—

REF - 0.250

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