HYB18T512400B2C datasheet(32/69 Pages) QIMONDA

32 / 69 page

Internet Data Sheet

Rev. 1.12, 2007-05

10062006-YPTZ-CDR7

HY[B/I]18T512[40/80/16]0B2[C/F](L)

512-Mbit Double-Data-Rate-Two SDRAM

TABLE 28

Differential DC and AC Input and Output Logic Levels

FIGURE 5

Differential DC and AC Input and Output Logic Levels Diagram

Symbol

Parameter

Min.

Max.

Unit

Note

IN(dc)

DC input signal voltage

–0.3

DDQ + 0.3

—

IN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.

ID(dc)

DC differential input voltage

0.25

DDQ + 0.6

—

ID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc).

ID(ac)

AC differential input voltage

0.5

DDQ + 0.6

ID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac).

IX(ac)

AC differential cross point input voltage

0.5

× V

DDQ – 0.175

0.5

× V

DDQ + 0.175

4) The value of

IX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac)

indicates the voltage at which differential input signals must cross.

OX(ac)

AC differential cross point output voltage 0.5

× V

DDQ – 0.125

0.5

× V

DDQ + 0.125

5) The value of

OX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac)

indicates the voltage at which differential input signals must cross.

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