HYB18T512400B2C datasheet(41/69 Pages) QIMONDA

41 / 69 page

Internet Data Sheet

Rev. 1.12, 2007-05

10062006-YPTZ-CDR7

HY[B/I]18T512[40/80/16]0B2[C/F](L)

512-Mbit Double-Data-Rate-Two SDRAM

Timing Characteristics

This chapter contains speed grade definition, AC timing parameter and ODT tables.

7.1

Speed Grade Definitions

All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications (

CK = 5ns with tRAS = 40ns).

TABLE 41

Speed Grade Definition Speed Bins for DDR2–800

Speed Grade

DDR2–800D

DDR2–800E

Unit

Note

QAG Sort Name

–25F

–2.5

CAS-RCD-RP latencies

5–5–5

6–6–6

Parameter

Symbol

Min.

Max.

Min.

Max.

—

Clock Frequency

@ CL = 3

1)2)3)4)

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal

OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements”.

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS,

RDQS / RDQS is defined .

3) Inputs are not recognized as valid until

REF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.

4) The output timing reference voltage level is

TT.

@ CL = 4

3.75

1)2)3)4)

@ CL = 5

2.5

1)2)3)4)

@ CL = 6

2.5

1)2)3)4)

Row Active Time

RAS

70000

1)2)3)4)5)

RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.

Row Cycle Time

57.5

—

1)2)3)4)

RAS-CAS-Delay

RCD

12.5

—

1)2)3)4)

Row Precharge Time

12.5

—

1)2)3)4)

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