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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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HYB18T512400B2C Scheda tecnica(PDF) 52 Page - Qimonda AG |
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HYB18T512400B2C Scheda tecnica(HTML) 52 Page - Qimonda AG |
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52 / 69 page  Internet Data Sheet Rev. 1.12, 2007-05 52 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM TABLE 47 DRAM Component Timing Parameter by Speed Grade - DDR2–533 Parameter Symbol DDR2–533 Unit Note1)2)3)4)5) 6) Min. Max. DQ output access time from CK / CK t AC –500 +500 ps CAS A to CAS B command period t CCD 2— t CK CK, CK high-level width t CH 0.45 0.55 t CK CKE minimum high and low pulse width t CKE 3— t CK CK, CK low-level width t CL 0.45 0.55 t CK Auto-Precharge write recovery + precharge time t DAL WR + t RP — t CK 7)17) Minimum time clocks remain ON after CKE asynchronously drops LOW t DELAY t IS + tCK + tIH –– ns 8) DQ and DM input hold time (differential data strobe) t DH(base) 225 –– ps 9) DQ and DM input hold time (single ended data strobe) t DH1(base) –25 — ps 10) DQ and DM input pulse width (each input) t DIPW 0.35 — t CK DQS output access time from CK / CK t DQSCK –450 +450 ps DQS input low (high) pulse width (write cycle) t DQSL,H 0.35 — t CK DQS-DQ skew (for DQS & associated DQ signals) t DQSQ — 300 ps 10) Write command to 1st DQS latching transition t DQSS – 0.25 + 0.25 t CK DQ and DM input setup time (differential data strobe) t DS(base) 100 — ps 10) DQ and DM input setup time (single ended data strobe) t DS1(base) –25 — ps 10) DQS falling edge hold time from CK (write cycle) t DSH 0.2 — t CK DQS falling edge to CK setup time (write cycle) t DSS 0.2 — t CK Clock half period t HP MIN. ( t CL, tCH) 11) Data-out high-impedance time from CK / CK t HZ — t AC.MAX ps 12) Address and control input hold time t IH(base) 375 — ps 10) Address and control input pulse width (each input) t IPW 0.6 — t CK Address and control input setup time t IS(base) 250 — ps 10) DQ low-impedance time from CK / CK t LZ(DQ) 2 × t AC.MIN t AC.MAX ps 13) DQS low-impedance from CK / CK t LZ(DQS) t AC.MIN t AC.MAX ps 13) Mode register set command cycle time t MRD 2— t CK OCD drive mode output delay t OIT 012 ns Data output hold time from DQS t QH t HP –tQHS —— Data hold skew factor t QHS — 400 ps Average periodic refresh Interval t REFI —7.8 µs 13)14) |
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