TMP89FS60 datasheet(34/410 Pages) TOSHIBA

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Page 20

2. CPU Core

2.3 System clock controller

TMP89FS60

RA001

2. Prescaler and divider

These circuits divide fcgck. The divided clocks are supplied to the timer counter, the time

base timer and other peripheral circuits.

When both SYSCR1<DV9CK> and SYSCR2<SYSCK> are "0", the input clock to stage 9

of the divider becomes the output of stage 8 of the divider.

When SYSCR1<DV9CK> or SYSCR2<SYSCK> is "1", the input clock to stage 9 of the

divider becomes fs/4. When SYSCR2<SYSCK> is "1", the outputs of stages 1 to 8 of the

divider and prescaler are stopped.

The prescaler and divider are cleared to "0" at a reset and at the end of the warm-up opera-

tion that follows the release of STOP mode.

3. Machine cycle

Instruction execution is synchronized with the main system clock (fm).

The minimum instruction execution unit is called a "machine cycle". One machine cycle

corresponds to one main system clock.

There are a total of 11 different types of instructions for the TLCS-870/C1 Series: 10 types

ranging from 1-cycle instructions, which require one machine cycle for execution, to 10-

cycle instructions, which require 10 machine cycles for execution, and 13-cycle instructions,

which require 13 machine cycles for execution.

2.3.4

Warm-up counter

The warm-up counter is a circuit that counts the high-frequency clock (fc) and the low-frequency clock (fs),

and it consists of a source clock selection circuit, a 3-stage frequency division circuit and a 14-stage counter.

The warm-up counter is used to secure the time after a power-on reset is released before the supply voltage

becomes stable and secure the time after the STOP mode is released or the operation mode is changed before

the oscillation by the oscillation circuit becomes stable.

Figure 2-6 Warm-up Counter Circuit

Clock for high-frequency clock

oscillation circuit (fc)

Clock for low-frequency clock

oscillation circuit (fs)

Com-

parator

WUCDR

SYSCR2

SYSCR1

WUCCR

Enable/disable counting up

XEN XTEN

STOP

INTWUC interrupt

Enable CPU operation

WUCSEL

WUCDIV

WUCRST

Warm-up counter

controller

1 2 3 4 5 6 7 8 9 10 11 12 1314

0 1 2 3 4 5 6 7

1 2 3

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