TMP89FS60 datasheet(30/410 Pages) TOSHIBA

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Page 16

2. CPU Core

2.3 System clock controller

TMP89FS60

RA001

Note 3: If the STOP mode is activated with SYSCR1<OUTEN> set at "0", the port internal input is fixed to "0". Therefore, an exter-

nal interrupt may be set at the falling edge, depending on the pin state when the STOP mode is activated.

Note 4: The P11 pin is also used as the STOP pin. When the STOP mode is activated, the pin reverts to high impedance state and

is put in input mode, regardless of the state of SYSCR1<OUTEN>.

Note 5: Writing of the second byte data will be executed improperly if the operation is switched to the STOP state by an instruc-

tion, such as LDW, which executes 2-byte data transfer at a time.

Note 6: Don't set SYSCK1<DV9CK> to "1" before the oscillation of the low-frequency clock oscillation circuit becomes stable.

Note 7: In the SLOW1/2 or SLEEP1 mode, fs/4 is input to stage 9 of the divider, regardless of the state of SYSCR1< DV9CK >.

Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]

Note 2: WDT: Watchdog timer, TG: Timing generator

Note 3: Don't set both SYSCR2<IDLE> and SYSCR2<TGHALT> to "1" simultaneously.

Note 4: Writing of the second byte data will be executed improperly if the operation is switched to the IDLE state by an instruction,

such as LDW, which executes 2-byte data transfer at a time.

Note 5: When the IDLE1/2 or SLEEP1 mode is released, SYSCR2<IDLE> is cleared to "0" automatically.

Note 6: When the IDLE0 or SLEEP0 mode is released, SYSCR2<TGHALT> is cleared to "0" automatically.

Note 7: Bits 7, 1 and 0 of SYSCR2 are read as "0".

Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz]

Note 2: WUCCR<WUCRST> is cleared to "0" automatically, and need not be cleared to "0" after being set to "1".

Note 3: Bits 7 to 4 of WUCCR are read as "0". Bit 0 is read as "1".

Note 4: Before starting the warm-up counter operation, set the source clock and the frequency division rate at WUCCR and set

the warm-up time at WUCDR.

System control register 2

SYSCR2

(0x0FDD)

76543

210

Bit Symbol

XEN

XTEN

SYSCK

IDLE

TGHALT

Read/Write

R/W

After reset

01000

000

XEN

Controls the high-frequency clock

oscillation circuit

0 :

1 :

Stop oscillation

Continue or start oscillation

XTEN

Controls the low-frequency clock

oscillation circuit

0 :

1 :

Stop oscillation

Continue or start oscillation

SYSCK

Selects a system clock

0 :

1 :

Gear clock (fcgck) (NORMAL1/2 or IDLE1/2 mode)

Low-frequency clock (fs/4) (SLOW1/2 or SLEEP1 mode)

IDLE

CPU and WDT control

(IDLE1/2 or SLEEP1 mode)

0 :

1 :

Operate the CPU and the WDT

Stop the CPU and the WDT (Activate IDLE1/2 or SLEEP1 mode)

TGHALT

TG control

(IDLE0 or SLEEP0 mode)

0 :

1 :

Enable the clock supply from the TG to all the peripheral circuits

Disable the clock supply from the TG to the peripheral circuits except the

TBT (Activate IDLE0 or SLEEP0 mode)

Warm-up counter control register

WUCCR

(0x0FCD)

76543

210

Bit Symbol

WUCRST

WUCDIV

WUCSEL

Read/Write

R/W

After reset

00001

101

WUCRST

Resets and stops the warm-up

counter

0 :

1 :

Clear and stop the counter

WUCDIV

Selects the frequency division of the

warm-up counter source clock

00 :

01 :

10 :

11 :

Source clock

Source clock / 2

Source clock / 22

Source clock / 23

WUCSEL

Selects the warm-up counter

source clock

0 :

1 :

Select the high-frequency clock (fc)

Select the low-frequency clock (fs)

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