TMP89FS60 datasheet(74/410 Pages) TOSHIBA

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3. Interrupt Control Circuit

3.6 Software Interrupt (INTSW)

TMP89FS60

RA003

3.6

Software Interrupt (INTSW)

Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW

is the top-priority interrupt).

Use the SWI instruction only for address error detection or for debugging described below.

3.6.1

Address error detection

0xFF is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent

memory address. Code 0xFF is an SWI instruction, so a software interrupt is generated and an address error is

detected. The address error detection range can be further expanded by writing 0xFF to unused areas in the pro-

gram memory.

3.6.2

Debugging

Debugging efficiency can be increased by placing the SWI instruction at the software break point setting

address.

3.7

Undefined Instruction Interrupt (INTUNDEF)

When the CPU tries to fetch and execute an instruction that is not defined, INTUNDEF is generated and starts the

interrupt processing. INTUNDEF is accepted even if another non-maskable interrupt is in process. The current pro-

cess is discontinued and the INTUNDEF interrupt process starts soon after it is requested.

Note: The undefined instruction interrupt (INTUNDEF) forces the CPU to jump into the interrupt vector address, as soft-

ware interrupt (SWI) does.

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