TMP89FS60 datasheet(65/410 Pages) TOSHIBA

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Page 51

TMP89FS60

RA003

3.3

Interrupt Enable Register (EIR)

The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable

interrupts (software interrupt, undefined instruction interrupt and watchdog interrupt). Non-maskable interrupts are

accepted regardless of the contents of the EIR.

The EIR consists of the interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These

registers are located at addresses 0x003A, 0x003B, 0x003C, 0x003D in the SFR area, and they can be read and writ-

ten by instructions (including read-modify-write instructions such as bit manipulation or operation instructions).

3.3.1

Interrupt master enable flag (IMF)

The interrupt master enable flag (IMF) enables and disables the acceptance of all maskable interrupts. Clear-

ing the IMF to "0" disables the acceptance of all maskable interrupts. Setting the IMF to "1" enables the accep-

tance of the interrupts that are specified by the individual interrupt enable flags.

When an interrupt is accepted, the IMF is stacked and then cleared to "0", which temporarily disables the

subsequent maskable interrupts. After the interrupt service routine is executed, the stacked data, which was the

status before interrupt acceptance, reloaded on the IMF by return interrupt instruction [RETI]/[RETN].

The IMF is located on bit 0 in EIRL (Address: 0x03A in SFR), and can be read and written by instructions.

The IMF is normally set and cleared by [EI] and [DI] instructions respectively. During reset, the IMF is initial-

ized to "0".

3.3.2

Individual interrupt enable flags (EF27 to EF4)

Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding

bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" dis-

ables acceptance.

During reset, all the individual interrupt enable flags are initialized to "0" and no maskable interrupts are

accepted until the flags are set to "1".

Note:In the main program, before manipulating the interrupt enable flag (EF), be sure to clear the master enable

flag (IMF) to "0" (Disable interrupt by DI instruction). Then set the IMF to "1" as required after operating the EF

(Enable interrupt by EI instruction).

In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally.

However, if using multiple interrupt in the interrupt service routine, manipulate the EF before setting the IMF to

"1".

Example: Enables interrupts individually and sets IMF

; IMF

← 0

LDW

(EIRL), 0y1110100010100000

;

EF15 to EF13, EF11, EF7, EF5

← 1

Note: IMF should not be set.

; IMF

← 1

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