TMP89FS60 datasheet(70/410 Pages) TOSHIBA

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Page 56

3. Interrupt Control Circuit

3.5 Interrupt Sequence

TMP89FS60

RA003

3.5

Interrupt Sequence

An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to

“0”

by resetting or an instruction. Interrupt acceptance sequence requires 8-machine cycles after the completion of

the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI]

(for maskable interrupts) or [RETN] (for non-maskable interrupts).

3.5.1

Initial Setting

Using an interrupt requires specifying an SP (stack pointer) for it in advance. The SP is a 16-bit register

pointing at the start address of a stack. The SP is post-decremented when a subroutine call or a push instruction

is executed or when an interrupt request is accepted. It is pre-incremented when a return or pop instruction is

executed. Therefore, the stack becomes deeper toward lower stack location addresses. Be sure to reserve a

stack area having an appropriate size based on the SP setting.

The SP is initialized to 00FFH after a reset. If you need to change the SP, do so right after a reset or when the

interrupt master enable flag (IMF) is “0”.

3.5.2

Interrupt acceptance processing

Interrupt acceptance processing is packaged as follows.

1. The interrupt master enable flag (IMF) is cleared to “0” in order to disable the acceptance of any fol-

lowing interrupt.

2. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.

3. The contents of the program counter (PC) and the program status word, including the interrupt master

enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Mean-

while, the stack pointer (SP) is decremented by 3.

4. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the

vector table, is transferred to the program counter.

5. The instruction stored at the entry address of the interrupt service program is executed.

Note:When the contents of PSW are saved on the stack, the contents of register bank and IMF are also saved.

Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt

service program

Figure 3-2 Vector table address and Entry address

Example :SP setting

SP, 023FH

; SP = 023FH

SP, SP+04H

; SP = SP + 04H

ADD

SP, 0010H

; SP = SP + 0010H

0x03

0xFFF4

0xFFF5

Vector table address

0xD2

0x0F

0xD203

0xD204

Vector table address

0x06

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