TMP89FS60 datasheet(58/410 Pages) TOSHIBA

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Page 44

2. CPU Core

2.4 Reset Control Circuit

TMP89FS60

RA001

2.4.4.8

Internal factor reset detection status register

By reading the internal factor reset detection status register IRSTSR after the release of an internal fac-

tor reset, except the power-on reset, the factor which causes a reset can be detected.

The internal factor reset detection status register is initialized by an external reset input or power-on

reset.

Set IRSTSR<FCLR> to "1" and write 0x71 to SYSCR4. This enables IRSTSR<FCLR> and the internal

factor reset detection status register is clear to "0". IRSTSR<FCLR> is cleared to "0" automatically after

initializing the internal factor reset detection status register.

Note 1: Care must be taken in system designing since the IRSTSR may not fulfill its functions due to disturb-

ing noise and other effects.

Note 2: After IRSTSR<FCLR> is modified, SYSCR4 should be written 0x71 (Enable code for

IRSTSR<FCLR> in NORMAL mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise,

IRSTSR<FCLR> may be enabled at unexpected timing.

2.4.4.9

How to use the external reset input pin as a port

To use the external reset input pin as a port, keep the external reset input pin at the "H" level until the

power is turned on and the warm-up operation that follows reset release is finished.

After the warm-up operation that follows reset release is finished, set P1PU0 to "1" and P1CR0 to "0",

and connect a pull-up resistor for a port. Then set SYSCR3<RSTDIS> to "1" and write 0xB2 to SYSCR4.

This disables the external reset function and makes the external reset input pin usable as a normal port.

To use the pin as an external reset pin when it is used as a port, set P1PU0 to "1" and P1CR0 to "0" and

connect the pull-up resistor to put the pin to the input mode. Then clear SYSCR3<RSTDIS> to "0" and

write 0xB2 to SYSCR4. This enables the external reset function and makes the pin usable as the external

reset input pin.

Note 1: If you switch the external reset input pin to a port or switch the pin used as a port to the external reset

input pin, do it when the pin is stabilized at the "H" level. Switching the pin function when the "L" level

is input may cause a reset.

Note 2: If the external reset input is used as a port, the statement which clears SYSCR3<RSTDIS> to "0" is

not written in a program. By the abnormal execution of program, the external reset input set as a port

may be changed as the external reset input at unexpected timing.

Note 3: After SYSCR3<RSTDIS> is modified, SYSCR4 should be written 0xB2 (Enable code for

SYSCR3<RSTDIS>) in NORMAL1 mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise,

SYSCR3<RSTDIS> may be enabled at unexpected timing.

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