TMP89FS60 datasheet(91/410 Pages) TOSHIBA

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Page 77

TMP89FS60

RA000

Note:The 8-bit up counter source clock operates out of synchronization with WDCTR<WDTEN>. Therefore, the first

overflow time of the 8-bit up counter after WDCTR<WDTEN> is set to "1" may get shorter by a maximum of 1

source clock. The 8-bit up counter must be cleared within a period of the overflow time minus 1 source clock

cycle.

5.3.4

Setting an overflow detection signal of the 8-bit up counter

WDCTR<WDTOUT> selects a signal to be generated when the overflow of the 8-bit up counter is detected.

1. When the watchdog timer interrupt request signal is selected (when WDCTR<WDTOUT> is "0")

Releasing WDCTR<WDTOUT> to "0" causes a watchdog timer interrupt request signal to occur

when the 8-bit up counter overflows.

A watchdog timer interrupt is a non-maskable interrupt, and its request is always accepted, regard-

less of the interrupt master enable flag (IMF) setting.

Note: When a watchdog timer interrupt is generated while another interrupt, including a watchdog timer interrupt, is already

accepted, the new watchdog timer interrupt is processed immediately and the preceding interrupt is put on hold. Therefore,

if watchdog timer interrupts are generated continuously without execution of the RETN instruction, too many levels of nest-

ing may cause a malfunction of the microcontroller.

2. When the watchdog timer reset request signal is selected (when WDCTR<WDTOUT> is "1")

Setting WDCTR<WDTOUT> to "1" causes a watchdog timer reset request signal to occur when

the 8-bit up counter overflows.

This watchdog timer reset request signal resets the TMP89FS60 and starts the warm-up operation.

5.3.5

Writing the watchdog timer control codes

The watchdog timer control codes are written into WDCDR.

By writing 0x4E (clear code) into WDCDR, the 8-bit up counter is cleared to "0" and continues counting the

source clock.

When WDCTR<WDTEN> is "0", writing 0xB1 (disable code) into WDCDR disables the watchdog timer

operation.

To prevent the 8-bit up counter from overflowing, clear the 8-bit up counter in a period shorter than the over-

flow time of the 8-bit up counter and within the clear time.

By designing the program so that no overflow will occur, the program malfunctions and deadlock can be

detected through interrupts generated by watchdog timer interrupt request signals.

By applying a reset to the microcomputer using watchdog timer reset request signals, the CPU can be

restored from malfunctions and deadlock.

Note:If the overflow of the 8-bit up counter and writing of 0x4E (clear code) into WDCDR occur simultaneously, the

8-bit up counter is cleared preferentially and the overflow detection is not executed.

Example: When WDCTR<WDTEN> is "0", set the watchdog timer detection time to 220/fcgck [s], set the counter clear

time to half of the overflow time, and allow a watchdog timer reset request signal to occur if a malfunction is

detected.

(WDCTR), 0y00110011

; WDTW

←10, WDTT←01, WDTOUT←1

Clear the 8-bit up counter at a point after

half of its overflow time and within a peri-

od of the overflow time minus 1 source

clock cycle.

(WDCDR), 0x4E

; Clear the 8-bit up counter

Clear the 8-bit up counter at a point after

half of its overflow time and within a peri-

od of the overflow time minus 1 source

clock cycle.

(WDCDR), 0x4E

; Clear the 8-bit up counter

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