TMP89FS60 datasheet(33/410 Pages) TOSHIBA

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Page 19

TMP89FS60

RA001

Immediately after reset release, the gear clock (fcgck) becomes the clock that is a quarter of the high-

frequency clock (fc).

Note: Don't change CGCR<FCGCKSEL> in the SLOW mode. This may stop the gear clock (fcgck) from

being changed.

2.3.3.3

Timing generator

The timing generator is a circuit that generates system clocks to be supplied to the CPU core and the

peripheral circuits, from the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock

(fs). The timing generator has the following functions:

1. Generation of the main system clock (fm)

2. Generation of clocks for the timer counter, the time base timer and other peripheral circuits

Figure 2-5 Configuration of Timing Generator

(1)

Configuration of timing generator

The timing generator consists of a main system clock generator, a prescaler, a 21-stage divider and

a machine cycle counter.

1. Main system clock generator

This circuit selects the gear clock (fcgck) or the clock that is a quarter of the low-frequency

clock (fs) for the main system clock (fm) to operate the CPU core.

Clearing SYSCR2<SYSCK> to "0" selects the gear clock (fcgck). Setting it to "1" selects

the clock that is a quarter of the low-frequency clock (fs).

It takes a certain period of time after SYSCR2<SYSCK> is changed before the main sys-

tem clock is switched. If the currently operating oscillation circuit is stopped before the main

system clock is switched, the internal condition becomes as shown in Table 2-1 and a system

clock reset occurs. For details of clock switching, refer to "2.3.6 Operation Mode Control".

Table 2-2

Gear Clock (fcgck)

CGCR<FCGCKSEL>

fcgck

fc / 4

fc / 2

Reserved

Main system clock generator

Machine cycle counter

SYSCR2<SYSCK>

SYSCR1<DV9CK>

Gear clock fcgck

Prescaler

Divider

Multiplexer

Timer counter, time base timer and other peripheral circuits

Divider

Main system clock

A quarter of the basic clock

for the low-frequency clock

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