TMP89FS60 datasheet(29/410 Pages) TOSHIBA

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Page 15

TMP89FS60

RA001

2.3

System clock controller

2.3.1

Configuration

The system clock controller consists of a clock generator, a clock gear, a timing generator, a warm-up

counter and an operation mode control circuit.

Figure 2-3 System Clock Controller

2.3.2

Control

The system clock controller is controlled by system control register 1 (SYSCR1), system control register 2

(SYSCR2), the warm-up counter control register (WUCCR), the warm-up counter data register (WUCDR) and

the clock gear control register (CGCR).

Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]

Note 2: Bits 2, 1 and 0 of SYSCR1 are read as "0". Bit 3 is read as "1".

System control register 1

SYSCR1

(0x0FDC)

76543

210

Bit Symbol

STOP

RELM

OUTEN

DV9CK

Read/Write

R/W

RRRR

After reset

00001

000

STOP

Activates the STOP mode

0 :

1 :

Operate the CPU and the peripheral circuits

Stop the CPU and the peripheral circuits (activate the STOP mode)

RELM

Selects the STOP mode release

method

0 :

1 :

Edge-sensitive release mode (Release the STOP mode at the rising edge

of the STOP mode release signal)

Level-sensitive release mode (Release the STOP mode at the "H" level of

the STOP mode release signal)

OUTEN

Selects the port output state in the

STOP mode

0 :

1 :

High impedance

Output hold

DV9CK

Selects the input clock to stage 9 of

the divider

0 :

1 :

fcgck/29

fs/4

Operation mode

control circuit

XTIN

XTOUT

Clock generator

System clock

INTWUC interrupt

System control register

Oscillation/stop control

Low-frequency clock

oscillation circuit

High-frequency

clock oscillation

circuit

XIN

XOUT

Timing

generator

fcgck

1/4

SYSCR1

SYSCR2

TBTCR

WUCCR

WUCDR

Clock gear control register

FCGCKSEL

STOP

DV9CK

XEN/XTEN

Warm-up counter

Clock gear

(x1/4,x1/2,x1)

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