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TMP89FS60 Scheda tecnica(PDF) 11 Page - Toshiba Semiconductor |
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TMP89FS60 Scheda tecnica(HTML) 11 Page - Toshiba Semiconductor |
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11 / 410 page ![]() vii 18.4.8 Interrupt service request and release ................................................................................................. 274 18.4.9 Setting of serial bus interface mode ................................................................................................... 274 18.4.10 Software reset................................................................................................................................... 274 18.4.11 Arbitration lost detection monitor ...................................................................................................... 275 18.4.12 Slave address match detection monitor............................................................................................ 276 18.4.13 GENERAL CALL detection monitor .................................................................................................. 277 18.4.14 Last received bit monitor................................................................................................................... 277 18.4.15 Slave address and address recognition mode specification............................................................. 277 18.5 Data Transfer of I2C Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 18.5.1 Device initialization ............................................................................................................................. 278 18.5.2 Start condition and slave address generation..................................................................................... 278 18.5.3 1-word data transfer............................................................................................................................ 279 18.5.3.1 When SBI0SR2<MST> is "1" (Master mode) 18.5.3.2 When SBI0SR2<MST> is "0" (Slave mode) 18.5.4 Stop condition generation ................................................................................................................... 283 18.5.5 Restart ................................................................................................................................................ 283 18.6 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 18.7 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 19. Key-on Wakeup (KWU) 19.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 19.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 19.3 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 20. 10-bit AD Converter (ADC) 20.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 20.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 20.3 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 20.3.1 Single mode........................................................................................................................................ 298 20.3.2 Repeat mode ...................................................................................................................................... 298 20.3.3 AD operation disable and forced stop of AD operation....................................................................... 299 20.4 Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 20.5 Starting STOP/IDLE0/SLOW Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 20.6 Analog Input Voltage and AD Conversion Result . . . . . . . . . . . . . . . . . . . . . . . 301 20.7 Precautions about the AD Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 20.7.1 Analog input pin voltage range ........................................................................................................... 302 20.7.2 Analog input pins used as input/output ports...................................................................................... 302 20.7.3 Noise countermeasure........................................................................................................................ 302 21. Flash Memory 21.1 Flash Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 21.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 21.2.1 Flash memory command sequence execution and toggle control (FLSCR1 <FLSMD>) ................... 307 21.2.2 Flash memory area switching (FLSCR1<FAREA>)............................................................................ 308 21.2.3 RAM area switching (SYSCR3<RAREA>).......................................................................................... 310 21.2.4 BOOTROM area switching (FLSCR1<BAREA>)................................................................................ 310 21.2.5 Flash memory standby control (FLSSTB<FSTB>) ............................................................................. 311 21.2.6 Port input control register (SPCR<PIN0, PIN1>) ................................................................................ 312 21.3 Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 21.3.1 Byte program ...................................................................................................................................... 314 21.3.2 Sector erase (4-kbyte partial erase) ................................................................................................... 315 21.3.3 Chip erase (all erase) ......................................................................................................................... 316 |
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