TMP89FS60 datasheet(27/410 Pages) TOSHIBA

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Page 13

TMP89FS60

RA001

2.2.2.1

SFR

The SFR is mapped to 0x0000 to 0x003F (SFR1), 0x0F00 to 0x0FFF (SFR2) and 0x0E40 to 0x0EFF

(SFR3) in the data area after reset release.

Note: Don't access the reserved SFR.

2.2.2.2

RAM

The RAM is mapped to 0x0040 to 0x0C3F in the data area after reset release.

Note: The contents of the RAM become unstable when the power is turned on and immediately after a reset

is released. To execute the program by using the RAM, transfer the program to be executed in the ini-

tialization routine.

2.2.2.3

BOOTROM

The BOOTROM is not mapped in the code area or the data area after reset release.

Note: The flash memory control register 1 has a double-buffer structure comprised of the register FLSCR1 and a shift register.

Writing "0xD5" to the register FLSCR2 allows a register setting to be reflected and take effect in the shift register. This

means that a register setting value does not take effect until "0xD5" is written to the register FLSCR2. The value of the shift

Example: RAM initialization program

HL, RAM_TOP_ADDRESS

; Head of address of the RAM to be initialized

A, 0x00

; Initialization data

BC, BYTE_OF_CLEAR_BYTES

; Number of bytes of RAM to be initialized -1

CLR_RAM:

(HL), A

; Initialization of the RAM

INC

; Initialization address increment

DEC

; Have all the RAMs been initialized?

JRS

F, CLR_RAM

Setting FLSMD<BAREA> to "1" maps the BOOTROM to 0x1000 to 0x17FF in the code area and to

0x1000 to 0x17FF in the data area. The BOOTROM can be easily written into the Flash by using the Ap-

plication Programming Interface (API) integrated in the BOOTROM.

Note1:

Only the first 2 Kbytes of the BOOTROM are mapped in the memory map, except in the serial PROM

mode.

Flash memory control register 1

FLSCR1

(0x0FD0)

76543

210

Bit Symbol

(FLSMD)

BAREA

(FAREA)

(ROMSEL)

Read/Write

R/W

After reset

01000

000

BAREA

Specifies mapping of the

BOOTROM in the code and data

areas

0 :

1 :

The BOOTROM is not mapped to 0x1000 to 0x17FF in the code area and

to 0x1000 to 0x17FF in the data area.

The BOOTROM is mapped to 0x1000 to 0x17FF in the code area and to

0x1000 to 0x17FF in the data area.

Flash memory control register 2

FLSCR2

76543

210

(0x0FD1)

Bit Symbol

CR1EN

Read/Write

After reset

*******

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