TMP89FS60 datasheet(49/410 Pages) TOSHIBA

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Page 35

TMP89FS60

RA001

(1)

Normal release mode (IMF, EF5, TBTCR<TBTEN> = "0")

The IDLE0 or SLEEP0 mode is released when the falling edge of the source clock selected at

TBTCR<TBTCK> is detected. After the IDLE0 or SLEEP0 mode is released, the operation is

restarted by the instruction that follows the IDLE0 or SLEEP0 mode start instruction.

When TBTCR<TBTEN> is "1", the time base timer interrupt latch is set.

(2)

Interrupt release mode (IMF, EF5, TBTCR<TBTEN> = "1")

The IDLE0 or SLEEP0 mode is released when the falling edge of the source clock selected at

TBTCR<TBTCK> is detected. After the release, the INTTBT interrupt processing is started.

Note 1: The IDLE0 or SLEEP0 mode is released to the NORMAL1 or SLOW1 mode by the asynchro-

nous internal clock selected at TBTCR<TBTCK>. Therefore, the period from the start to the

release of the mode may be shorter than the time specified at TBTCR<TBTCK>.

Note 2: When a watchdog timer interrupt is generated immediately before the IDLE0 or SLEEP0 mode

is started, the watchdog timer interrupt will be processed but the IDLE0 or SLEEP0 mode will

not be started.

2.3.6.4

SLOW mode

The SLOW mode is controlled by system control register 2 (SYSCR2).

(1)

Switching from the NORMAL2 mode to the SLOW1 mode

Set SYSCR2<SYSCK> to "1".

When a maximum of 2/fcgck + 10/fs [s] has elapsed since SYSCR2<SYSCK> is set to "1", the

main system clock (fm) is switched to fs/4.

After switching, wait for 2 machine cycles or longer, and then clear SYSCR2<XEN> to "0" to turn

off the high-frequency clock oscillator.

If the oscillation of the low-frequency clock (fs) is unstable, confirm the stable oscillation at the

warm-up counter before implementing the procedure described above.

Note 1: Be sure to follow this procedure to switch the operation from the NORMAL2 mode to the

SLOW1 mode.

Note 2: It is also possible to allow the basic clock for the high-frequency clock to oscillate continuously to

return to NORMAL2 mode. However, be sure to turn off the oscillation of the basic clock for the

high-frequency clock when the STOP mode is started from the SLOW mode.

Note 3: After switching SYSCR2<SYSCK>, be sure to wait for 2 machine cycles or longer before clear-

ing SYSCR2<XEN> to "0". Clearing it within 2 machine cycles causes a system clock reset.

Note 4: When the main system clock (fm) is switched, the gear clock (fcgck) is synchronized with the

clock that is a quarter of the basic clock (fs) for the low-frequency clock. For the synchronization,

fm is stopped for a period of 10/fs or shorter.

Figure 2-12 Switching of the Main System Clock (fm) (Switching from fcgck to fs/4)

Gear clock (fcgck)

When the rising edge of fcgck is

detected twice after SYSCR2<SYSCK>

is changed from 0 to 1, f is stopped

for synchronization.

When the rising edge of fs/4 is detected

twice after fm is stopped, fm is switched to fs.

Quarter of the low-frequency clock

(fs/4)

Main system clock

SYSCR2<SYSCK>

10/fs (max.)

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