TMP89FS60 datasheet(31/410 Pages) TOSHIBA

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Page 17

TMP89FS60

RA001

Note 1: Don't start the warm-up counter operation with WUCDR set at "0x00".

Note 1: fcgck: Gear clock [Hz], fc: High-frequency clock [Hz]

Note 2: Don't change CGCR<FCGCKSEL> in the SLOW mode.

Note 3: Bits 7 to 2 of CGCR are read as "0".

2.3.3

Functions

2.3.3.1

Clock generator

The clock generator generates the basic clock for the system clocks to be supplied to the CPU core and

peripheral circuits.

It contains two oscillation circuits: one for the high-frequency clock and the other for the low-frequency

clock.

The oscillation circuit pins are also used as ports P0. For the setting to use them as ports, refer to the

chapter of I/O Ports.

To use ports P00 and P01 as the high-frequency clock oscillation circuits (the XIN and XOUT pins), set

P0FC0 to "1" and then set SYSCR2<XEN> to "1".

To use ports P02 and P03 as the low-frequency clock oscillation circuits (the XTIN and XTOUT pins),

set P0FC2 to "1" and then set SYSCR2<XTEN> to "1".

The high-frequency (fc) clock and the low-frequency (fs) clock can easily be obtained by connecting an

oscillator between the XIN and XOUT pins and between the XTIN and XTOUT pins respectively.

Clock input from an external oscillator is also possible. In this case, external clocks are applied to the

XIN/XTIN pins and the XOUT/XTOUT pins are kept open.

Enabling/disabling the oscillation of the high-frequency clock oscillation circuit and the low-frequency

clock oscillation circuit and switching the pin function to ports are controlled by the software and hard-

ware.

The software control is executed by SYSCR2<XEN>, SYSCR2<XTEN> and the P0 port function con-

trol register P0FC.

Warm-up counter data register

WUCDR

(0x0FCE)

76543

210

Bit Symbol

WUCDR

Read/Write

R/W

After reset

01100

110

WUCDR

Warm-up time setting

Clock gear control register

CGCR

(0x0FCF)

76543

210

Bit Symbol

-----

FCGCKSEL

Read/Write

RRRRRR

R/W

After reset

00000

000

FCGCKSEL

Clock gear setting

00 :

01 :

10 :

11 :

fcgck = fc / 4

fcgck = fc / 2

fcgck = fc

Reserved

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