TMP89FS60 datasheet(44/410 Pages) TOSHIBA

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Page 30

2. CPU Core

2.3 System clock controller

TMP89FS60

RA001

2. Release by the key-on wakeup

The STOP mode is released by inputting the prescribed level to the key-on wakeup pin.

The level to release the STOP mode can be selected from "H" and "L".

For release by the key-on wakeup, refer to section "Key-on Wakeup".

3. Release by the voltage detection circuits

The STOP mode is released by the supply voltage detection by the voltage detection cir-

cuits.

To release the STOP mode by using the voltage detection circuits, set VDCR2<VDSS> to

"01" or "10".

If the voltage detection operation mode of the voltage detection circuits is set to generate

reset signals (when VDCR2<VDxMOD> is 1 (x=1 to 2)), the STOP mode is released and a

reset is applied as soon as the supply voltage becomes lower than the detection voltage.

When the supply voltage becomes equal to or higher than the detection voltage of the volt-

age detection circuits, the reset is released and the warm-up starts. After the warm-up is com-

pleted, the NORMAL1 mode becomes active.

If the voltage detection operation mode of the voltage detection circuits is set to generate

interrupt request signals (when VDCR2<VDxMOD> is 0 (x=1 to 2)), the STOP mode is

released when the supply voltage becomes equal to or higher than the detection voltage.

For details, refer to the section of the voltage detection circuits.

(3)

STOP mode release operation

The STOP mode is released in the following sequence:

1. Oscillation starts. For the oscillation start operation in each mode, refer to "Table 2-4 Oscil-

lation Start Operation at Release of the STOP Mode".

2. Warm-up is executed to secure the time required to stabilize oscillation. The internal opera-

tions remain stopped during warm-up. The warm-up time is set by the warm-up counter,

depending on the oscillator characteristics.

3. After the warm-up time has elapsed, the normal operation is restarted by the instruction that

follows the STOP mode start instruction. At this time, the prescaler and the divider of the

timing generator are cleared to "0".

Note: When the STOP mode is released with a low hold voltage, the following cautions must be

observed.

The supply voltage must be at the operating voltage level before releasing the STOP mode. The

RESET

pin input must also be "H" level, rising together with the supply voltage. In this case, if an

external time constant circuit has been connected, the RESET pin input voltage will increase at a

slower pace than the power supply voltage. At this time, there is a danger that a reset may occur

if the input voltage level of the RESET pin drops below the non-inverting high-level input voltage

(Hysteresis input).

Note:

If the key-on wakeup pin input becomes the opposite level to the release level after the

warm-up starts, the STOP mode is not restarted.

Note:

If the supply voltage becomes equal to or higher than the detection voltage within 1 ma-

chine cycle after SYSCR1<STOP> is set to "1", the STOP mode will not be released.

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