TMP89FS60 datasheet(41/410 Pages) TOSHIBA

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Page 27

TMP89FS60

RA001

2.3.6

Operation Mode Control

2.3.6.1

STOP mode

The STOP mode is controlled by system control register 1 (SYSCR1) and the STOP mode release sig-

nals.

(1)

Start the STOP mode

The STOP mode is started by setting SYSCR1<STOP> to "1". In the STOP mode, the following

states are maintained:

1. Both the high-frequency and low-frequency clock oscillation circuits stop oscillation and all

internal operations are stopped.

2. The data memory, the registers and the program status word are all held in the states in

effect before STOP mode was started. The port output latch is determined by the value of

SYSCR1<OUTEN>.

3. The prescaler and the divider of the timing generator are cleared to "0".

4. The program counter holds the address of the instruction 2 ahead of the instruction (e.g.,

[SET (SYSCR1).7]) which started the STOP mode.

(2)

Release the STOP mode

The STOP mode is released by the following STOP mode release signals. It is also released by a

reset by the RESET pin, a power-on reset and a reset by the voltage detection circuits. When a reset is

released, the warm-up starts. After the warm-up is completed, the NORMAL1 mode becomes active.

1. Release by the STOP pin

Table 2-3

Operation Modes and Conditions

Operation mode

Oscillation circuit

CPU core

Watchdog

timer

Time base

timer

Other periph-

eral circuits

Machine cycle time

High-fre-

quency

Low-fre-

quency

Single clock

RESET

Oscillation

Stop

Reset

1 / fcgck [s]

NORMAL1

Operate

IDLE1

Stop

IDLE0

Stop

STOP

Stop

Å|

Dual clock

NORMAL2

Oscillation

Operate with

the high fre-

quency

Operate with

the high/low

frequency

Operate

1 / fcgck [s]

IDLE2

Stop

SLOW2

Operate with

the low fre-

quency

Operate with

the low fre-

quency

4/ fs [s]

SLOW1

Stop

Operate with

the low fre-

quency

Operate with

the low fre-

quency

SLEEP1

Stop

SLEEP0

Stop

STOP

Stop

Å|

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