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TMP89FS60 Scheda tecnica(PDF) 92 Page - Toshiba Semiconductor |
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TMP89FS60 Scheda tecnica(HTML) 92 Page - Toshiba Semiconductor |
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92 / 410 page ![]() Page 78 5. Watchdog Timer (WDT) 5.3 Functions TMP89FS60 RA000 5.3.6 Reading the 8-bit up counter The counter value of the 8-bit up counter can be read by reading WDCNT. The stoppage of the 8-bit up counter can be detected by reading WDCNT at random times and comparing the value to the last read value. 5.3.7 Reading the watchdog timer status The watchdog timer status can be read at WDST. WDST<WDTST> is set to "1" when the watchdog timer operation is enabled, and it is cleared to "0" when the watchdog timer operation is disabled. WDST<WINTST2> is set to "1" when a watchdog timer interrupt request signal occurs due to the overflow of the 8-bit up counter. WDST<WINTST1> is set to "1" when a watchdog timer interrupt request signal occurs due to the operation for releasing the 8-bit up counter outside the clear time. You can know which factor has caused a watchdog timer interrupt request signal by reading WDST<WINTST2> and WDST<WINTST1> in the watchdog timer interrupt service routine. WDST<WINTST2> and WDST<WINTST1> are cleared to "0" when WDST is read. If WDST is read at the same time as the condition for turning WDST<WINTST2> or WDST<WINTST1> to "1" is satisfied, WDST<WINTST2> or WDST<WINTST1> is set to "1", rather than being cleared. Figure 5-4 Changes in the Watchdog Timer Status 8-bit up counter value When WDCTR<WDTW> is 10 Writing of 4EH (clear code) WDST<WINTST1> Watchdog timer interrupt request signal Interrupt request signal generated by clearing the 8-bit up counter outside the clear time Interrupt request signal generated by the overflow of the 8-bit up counter 00H 01H 3FH 40H 01H 7FH 80H BFH C0H FFH 00H FFH Clear time Outside the clear time Reading of WDST WDST<WINTST2> |
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