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TMP89FS60 Scheda tecnica(PDF) 6 Page - Toshiba Semiconductor |
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TMP89FS60 Scheda tecnica(HTML) 6 Page - Toshiba Semiconductor |
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6 / 410 page ![]() ii 3. Interrupt Control Circuit 3.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2 Interrupt Latches (IL27 to IL3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3 Interrupt Enable Register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.1 Interrupt master enable flag (IMF) .......................................................................................................... 51 3.3.2 Individual interrupt enable flags (EF27 to EF4) ...................................................................................... 51 3.4 Maskable Interrupt Priority Change Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.5 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.5.1 Initial Setting ........................................................................................................................................... 56 3.5.2 Interrupt acceptance processing............................................................................................................. 56 3.5.3 Saving/restoring general-purpose registers............................................................................................ 57 3.5.3.1 Using PUSH and POP instructions 3.5.3.2 Using data transfer instructions 3.5.3.3 Using a register bank to save/restore general-purpose registers 3.5.4 Interrupt return ........................................................................................................................................ 59 3.6 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.6.1 Address error detection .......................................................................................................................... 60 3.6.2 Debugging .............................................................................................................................................. 60 3.7 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.8 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4. External Interrupt control circuit 4.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.3.1 Low power consumption function ........................................................................................................... 67 4.3.2 External interrupt 0 ................................................................................................................................. 68 4.3.3 External interrupts 1/2/3.......................................................................................................................... 68 4.3.3.1 Interrupt request signal generating condition detection function 4.3.3.2 A noise canceller pass signal monitoring function when interrupt request signals are generated 4.3.3.3 Noise cancel time selection function 4.3.4 External interrupt 4 ................................................................................................................................. 69 4.3.4.1 Interrupt request signal generating condition detection function 4.3.4.2 A noise canceller pass signal monitoring function when interrupt request signals are generated 4.3.4.3 Noise cancel time selection function 4.3.5 External interrupt 5 ................................................................................................................................. 71 5. Watchdog Timer (WDT) 5.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.3.1 Setting of enabling/disabling the watchdog timer operation ................................................................... 75 5.3.2 Setting the clear time of the 8-bit up counter .......................................................................................... 76 5.3.3 Setting the overflow time of the 8-bit up counter .................................................................................... 76 5.3.4 Setting an overflow detection signal of the 8-bit up counter ................................................................... 77 5.3.5 Writing the watchdog timer control codes............................................................................................... 77 5.3.6 Reading the 8-bit up counter .................................................................................................................. 78 5.3.7 Reading the watchdog timer status ........................................................................................................ 78 6. Power-on Reset Circuit 6.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 |
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