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TMP89FS60 Scheda tecnica(PDF) 40 Page - Toshiba Semiconductor |
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TMP89FS60 Scheda tecnica(HTML) 40 Page - Toshiba Semiconductor |
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40 / 410 page ![]() Page 26 2. CPU Core 2.3 System clock controller TMP89FS60 RA001 2.3.5.4 Transition of operation modes Note 1: The NORMAL1 and NORMAL2 modes are generically called the NORMAL mode; the SLOW1 and SLOW2 modes are called the SLOW mode; the IDLE0, IDLE1 and IDLE2 modes are called the IDLE mode; and the SLEEP0 and SLEEP1 are called the SLEEP mode. Note 2: The mode is released by the falling edge of the source clock selected at TBTCR<TBTCK>. Figure 2-7 Operation Mode Transition Diagram IDLE0 mode RESET Warm-up that follows reset release NORMAL1 mode STOP NORMAL2 mode SLOW2 mode SLOW1 mode IDLE0 mode IDLE2 mode SLEEP1 mode SLEEP0 mode (a) Single-clock mode (b) Dual-clock mode SYSCR2<IDLE> = "1" SYSCR1<STOP> = "1" SYSCR2<IDLE> = "1" SYSCR1<STOP> = "1" SYSCR2<IDLE> = "1" SYSCR1<STOP> = "1" Interrupt Interrupt STOP mode release signal STOP mode release signal STOP mode release signal Interrupt SYSCR2<TGHA L T> = "1" SYSCR2<XTEN> = "0" SYSCR2<XTEN> = "1" SYSCR2<SYSCK> = "0" SYSCR2<SYSCK> = "1" SYSCR2<XEN> = "0" SYSCR2<TGHALT> = "1" Reset release Warm-up completed SYSCR2<XEN> = "1" (Note 2) (Note 2) |
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