TMP89FS60 datasheet(79/410 Pages) TOSHIBA

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Page 65

TMP89FS60

RA000

clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2,

wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.

Note 3: Interrupt requests may be generated when EINTCR1 is changed. Before doing such operation, clear the corresponding

interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from

NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the inter-

rupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/

fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.

Note 4: Bits 7 to 5 of EINTCR1 are read as "0".

Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]

Note 2: Interrupt requests may be generated during transition of the operation mode. Before changing the operation mode, clear

the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is

changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and

clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2,

wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.

Note 3: Interrupt requests may be generated when EINTCR2 is changed. Before doing such operation, clear the corresponding

interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from

NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the inter-

rupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/

fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.

Note 4: Bits 7 to 5 of EINTCR2 are read as "0".

External interrupt control register 2

EINTCR1

(0x0FD9)

76543

210

Bit Symbol

INT2LVL

INT2ES

INT2NC

Read/Write

RRRR

R/W

After reset

0000

INI2LVL

Noise canceller pass signal level

when the interrupt request signal is

generated for external interrupt 2

0 :

1 :

Initial state or signal level "L"

Signal level "H"

INT2ES

Selects the interrupt request gener-

ating condition for external interrupt

00 :

01 :

10 :

11 :

An interrupt request is generated at the rising edge of the noise canceller

pass signal

An interrupt request is generated at the falling edge of the noise canceller

pass signal

An interrupt request is generated at both edges of the noise canceller

pass signal

Reserved

INT2NC

Sets the noise canceller sampling

interval for external interrupt 2

NORMAL1/2, IDLE1/2

SLOW1/2, SLEEP1

00 :

01 :

10 :

11 :

fcgck [Hz]

fcgck / 22 [Hz]

fcgck / 23 [Hz]

fcgck / 24 [Hz]

00 :

01 :

10 :

11 :

fs/4 [Hz]

External interrupt control register 3

EINTCR3

(0x0FDA)

76543

210

Bit Symbol

INT3LVL

INT3ES

INT3NC

Read/Write

RRRR

R/W

After reset

0000

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