PIIX3 datasheet(106/122 Pages) INTEL

106 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

106

APICCS# is generated when the PCI memory cycle address matches the APIC’s programmed address and

the APICCS# function is enabled in the XBCS Register. The APIC address can be relocated by programming

the APIC Base Address Register (APICBASE).

APICCS# is only generated for PCI originated cycles and is not generated for ISA originated cycles. This PCI

cycle is forwarded to the ISA bus. To avoid address aliasing conflicts with other ISA devices, PIIX3 drives

SA[19:16] and LA[23:17] to 0 and drives SA[15:0] corresponding to PCI AD[15:2] and C/BE[3:0]#.

When the APICCS# function is enabled, the XOE#/XDIR# signals controlling the X-bus tranceiver and the

SOE#/SDIR signals controlling the IDE DD isolation transceiver are also enabled during accesses to the

IOAPIC.

The IOAPIC signals (APICCS#, APICREQ#, and APICACK#) are multiplexed with DD14, TESTIN#, and

PCIRST#, respectively. Figure 9 shows how these signals are connected in systems with and without the

IOAPIC device.

The internal IRQ0 signal can be routed to the external pin MIRQ0 using bit 5 in the MBIRQ Route Control

external IO-APIC. The secondary IDE device interrupt should then be routed to IRQ15.

PIIX3

DD14/APICCS#

TESTIN#/APICREQ#

PICRST#/APICACK#

I/O APIC

CS#

APICREQ#

APICACK#

RSTDRV

PCIRST#

RSTDRV

PIIX3

DD14/APICCS#

TESTIN#/APICREQ#

PICRST#/APICACK#

RSTDRV

TESTIN#

PCIRST#

Connect

RSTDRV

PIIX3 With I/O APIC

PIIX3 Without I/O APIC

apic_sys.drw

APIC_SYS

Figure 9. APIC Signal Connections

3.10.

INTR Signaling with Pentium® processor Local APIC in Virtual Wire Mode

The Pentium® processor with a Local APIC enabled in Virtual Wire (also called Through Local) mode

requires a minimum deassertion time on the INTR signal. The PIIX3 asserts INTR asynchronously in a

method compatible with the 8259A Programmable Interrupt Controller, which does not guarantee this

minimum deassertion time.

This only affects Pentium® processors which have a Local APIC and the Local APIC is in Virtual Wire mode

of operation. This results in the following system impacts:

Pentium® uni-processor system with no IO-APIC: No impact since the Pentium processor Local

APIC must be placed in Bypass mode of operation. This includes 430VX systems with PIIX3 and

430HX systems with PIIX3 but no IO-APIC.

PIIX3 Scheda tecnica(PDF) 106 Page - Intel Corporation

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