PIIX3 datasheet(109/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

109

3.12.1.

SMM MODE

SMM mode is invoked by asserting the SMI# signal to the CPU. The PIIX/PIIX3 provides a variety of

programmable events that can generate an SMI. When the CPU receives an SMI, it enters SMM mode and

executes SMM code out of SMRAM. Depending on the current state, the SMM code places the system in

either the Power On state or the Fast Off state. In the Power On state, the computer system operates

normally. In this state one of the four programmable events listed below can trigger an SMI.

A global idle timer called the Fast Off timer expires (an indication that the end user has not used the

computer for a programmed period of time).

The EXTSMI# pin is asserted.

The operating system issues an APM call.

3.12.2.

SMI SOURCES

The SMI# signal can be asserted by hardware interrupt events, the Fast Off Timer, an external SMI event

(EXTSMI#), and software events (via the APMC and APMS Registers). Enable/disable bits (in the SMIEN

can be globally enabled/disabled in the SMICNTL Register. Status of the individual events causing an SMI is

provided in the SMIREQ Register. For detailed information on the SMI control/status registers, refer to the

Hardware Interrupt Events

Hardware events (IRQ[12,8#,4,3,1] and the Fast Off Timer) are enabled/disabled from generating an SMI in

the SMIEN Register. When enabled, the occurrence of the corresponding hardware event generates an SMI

(asserts the SMI# signal), regardless of the current power state of the system.

Fast Off Timer

The Fast Off Timer is used to indicate (through an SMI) that the system has been idle for a programmed

period of time. The timer counts down from a programmed start value and when the count reaches 00h, can

generate an SMI. The timer decrement rate is programmable (via the SMICNTL Register) and is re-loaded

each time a system event occurs. This counter should not be programmed to 00h. System and break events

are described in the SEE Register.

EXTSMI#

The EXTSMI# input pin provides the system designer the capability to invoke SMM with external hardware.

For example, the EXTSMI# input could be connected to a "green button" permitting the user to enter the Fast

Off state by depressing a button. The EXTSMI# generation of an SMI is enabled/disabled in the SMIEN

For the PIIX3, the EXTSMI# signal can be used to provide a special protocol between the host-to-PCI bridge

and the PIIX3 (see MSTAT Register description, 6B-6Ah, function 0).

Software Events

Software events (accessing the APMx Registers) indicate that the OS is passing power management

information to the SMI handler. There are two Advanced Power Management (APM) registers — APM

Control (APMC) and APM Status (APMS) Registers. These registers permit software to generate an SMI; by

writing to the APMC Register. For example, the APMC can be used to pass an APM command between APM

OS and BIOS and the APMS Register could be used to pass data between the OS and the SMI handler.

PIIX3 Scheda tecnica(PDF) 109 Page - Intel Corporation