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PIIX3 Scheda tecnica(PDF) 111 Page - Intel Corporation |
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PIIX3 Scheda tecnica(HTML) 111 Page - Intel Corporation |
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111 / 122 page  E 82371FB (PIIX) AND 82371SB (PIIX3) 111 Some PCI devices may drive 3.3V friendly signals directly to 3.3V devices that are not 5V tolerant. If such signals are powered from the 5V supply they must be driven low when PCIRST# is asserted. Some of these signals may need to be driven high before CPURST is negated. PCIRST# is negated 1 ms to 2 ms before CPURST to allow time for this to occur. 3.13.1. HARDWARE STRAPPING OPTIONS For the PIIX/PIIX3, the SYSCLK signal is used during a hard reset to select the ISA clock divisor (sampled high for divisor of 3 – 25 MHz PCI operation. Sampled low for a divisor of 4 – 33 MHz or 30 MHz PCI operation). A 10K ohm resistor, jumperable as a pull up or pull down, on SYSCLK, can be used to configure divide-by-3 or divide-by-4 SYSCLK frequency. The logic level sensed on SYSCLK at reset configures the frequency. An alternate solution is using an open drain buffer enabled only during reset to drive the appropriate level on SYSCLK. For the PIIX, a strapping option on the TC during a hard reset selects between ISA DMA mode and an external DMA mode (sampled high for ISA DMA mode and low for external DMA mode). |
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