WM8281ECSSLASHR datasheet(48/392 Pages) CIRRUS

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WM8281

Rev 4.0

ANALOGUE LINE INPUT

Line inputs can be connected to the WM8281 in a similar manner to the microphone inputs described

above. Single-ended and differential modes are supported on each of the six analogue input paths.

The applicable mode (single-ended or differential) is selected using the INn_MODE registers, as

described later. Note that the mode is configurable for each stereo pair of inputs; the Left and Right

channels of any pair of inputs are always in the same mode.

The analogue line input configurations are illustrated in Figure 18 and Figure 19. Note that the

microphone bias (MICBIAS) is not used for line input connections.

GND

Line

To ADC

PGA

VMID

IN1xN,

IN2xN,

IN3xN

IN1xP,

IN2xP,

IN3xP

To ADC

PGA

VMID

IN1xN,

IN2xN,

IN3xN

IN1xP,

IN2xP,

IN3xP

Line

Figure 18 Single-Ended Line Input

Figure 19 Differential Line Input

DIGITAL MICROPHONE INPUT

Up to eight digital microphones can be connected to the WM8281. The digital microphone mode is

selected using the INn_MODE registers, as described later. Note that the mode is configurable for

each stereo pair of inputs; the Left and Right channels of any pair of inputs are always in the same

mode.

In digital microphone mode, two channels of audio data are multiplexed on the DMICDAT1,

DMICDAT2, DMICDAT3 or DMICDAT4 pins. Each of these stereo interfaces is clocked using the

respective DMICCLK1, DMICCLK2, DMICCLK3 or DMICCLK4 pin.

When digital microphone input is enabled, the WM8281 outputs a clock signal on the applicable

DMICCLKn pin(s). The DMICCLKn frequency is controlled by the respective INn_OSR register, as

described in Table 1. See Table 3 for details of the INn_OSR registers.

Note that, if the 768kHz DMICCLKn frequency is selected for one or more of the digital microphone

input paths, then the Input Path sample rate (all input paths) is valid in the range 8kHz to 16kHz only.

Note that the DMICCLKn frequencies noted in Table 1 assume that the SYSCLK frequency is a

multiple of 6.144MHz (SYSCLK_FRAC=0). If the SYSCLK frequency is a multiple of 5.6448MHz

(SYSCLK_FRAC=1), then the DMICCLKn frequencies will be scaled accordingly.

CONDITION

DMICCLK

n FREQUENCY

SIGNAL PASSBAND

INn_OSR = 00

1.536MHz

up to 20kHz

INn_OSR = 01

3.072MHz

up to 20kHz

INn_OSR = 10

6.144MHz

up to 96kHz

INn_OSR = 11

768kHz

up to 8kHz

Table 1 DMICCLK Frequency

The voltage reference for each digital microphone interface is selectable, using the INn_DMIC_SUP

registers. Each interface may be referenced to MICVDD, or to the MICBIAS1, MICBIAS2 or

MICBIAS3 levels.

A pair of digital microphones is connected as illustrated in Figure 20. The microphones must be

configured to ensure that the Left mic transmits a data bit when DMICCLK is high, and the Right mic

transmits a data bit when DMICCLK is low. The WM8281 samples the digital microphone data at the

end of each DMICCLK phase. Each microphone must tri-state its data output when the other

microphone is transmitting.

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