WM8281ECSSLASHR datasheet(68/392 Pages) CIRRUS

68 / 392 page

WM8281

Rev 4.0

Silence (mute) (00h)

AEC Loopback (08h)

IN1L signal path (10h)

IN1R signal path (11h)

IN2L signal path (12h)

IN2R signal path (13h)

IN3L signal path (14h)

IN3R signal path (15h)

IN4L signal path (16h)

IN4R signal path (17h)

AIF1 RX1 (20h)

AIF1 RX2 (21h)

AIF1 RX3 (22h)

AIF1 RX4 (23h)

AIF1 RX5 (24h)

AIF1 RX6 (25h)

AIF1 RX7 (26h)

AIF1 RX8 (27h)

AIF2 RX1 (28h)

AIF2 RX2 (29h)

AIF2 RX3 (2Ah)

AIF2 RX4 (2Bh)

AIF2 RX5 (2Ch)

AIF2 RX6 (2Dh)

AIF3 RX1 (30h)

AIF3 RX2 (31h)

SLIMbus RX1 (38h)

SLIMbus RX2 (39h)

SLIMbus RX3 (3Ah)

SLIMbus RX4 (3Bh)

SLIMbus RX5 (3Ch)

SLIMbus RX6 (3Dh)

SLIMbus RX7 (3Eh)

SLIMbus RX8 (3Fh)

Figure 24 Digital Core Inputs

DIGITAL CORE OUTPUT MIXERS

The digital core comprises multiple output paths. The output paths associated with AIF1, AIF2 and

AIF3 are illustrated in Figure 25. The output paths associated with OUT1, OUT2, OUT3, OUT4, OUT5

and OUT6 are illustrated in Figure 26. The output paths associated with the SLIMbus interface are

illustrated in Figure 27.

A 4-input mixer is associated with each output. The 4 input sources are selectable in each case, and

independent volume control is provided for each path.

The AIF1, AIF2 and AIF3 output mixer control registers (see Figure 25) are located at register

addresses R1792 (700h) through to R1935 (78Fh). The OUT1, OUT2, OUT3, OUT4, OUT5 and

OUT6 output mixer control registers (see Figure 26) are located at addresses R1664 (680h) through

to R1759 (6DFh). The SLIMbus output mixer control registers (see Figure 27) are located at

addresses R1984 (7C0h) through to R2047 (7FFh).

The full list of

digital mixer control registers is provided in the “Register Map” section (Register R1600

through to R3000). Generic register definitions are provided in Table 8.

The *_SRCn registers select the input source(s) for the respective mixers. Note that the selected input

source(s) must be configured for the same sample rate as the mixer to which they are connected.

Sample rate conversion functions are available to support flexible interconnectivity - see

“Asynchronous Sample Rate Converter (ASRC)” and “Isochronous Sample Rate Converter (ISRC)”.

The sample rate for the output signal paths is configured using the applicable OUT_RATE,

AIFn_RATE or SLIMTXn_RATE register - see Table 23. Note that sample rate conversion is required

when routing the output signal paths to any signal chain that is asynchronous and/or configured for a

different sample rate.

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