WM8281ECSSLASHR datasheet(73/392 Pages) CIRRUS

73 / 392 page

WM8281

Rev 4.0

The EQ1, EQ2, EQ3 and EQ4 mixer control registers (see Figure 29) are located at register

addresses R2176 (880h) through to R2207 (89Fh).

The full list of digital mixer control registers is provided in the “Register Map” section (Register R1600

through to R3000). Generic register definitions are provided in Table 8.

The *_SRCn registers select the input source(s) for the respective EQ processing blocks. Note that

the selected input source(s) must be configured for the same sample rate as the EQ to which they are

connected. Sample rate conversion functions are available to support flexible interconnectivity - see

“Asynchronous Sample Rate Converter (ASRC)” and “Isochronous Sample Rate Converter (ISRC)”.

The bracketed numbers in Figure 29

, eg. “(50h)” indicate the corresponding *_SRCn register setting

for selection of that signal as an input to another digital core function.

The sample rate for the EQ function is configured using the FX_RATE register - see Table 23. Note

that the EQ, DRC and LHPF functions must all be configured for the same sample rate.

The EQ function supports audio sample rates in the range 8kHz to 192kHz. When the DRC is

enabled, the maximum sample rate for the EQ, DRC and LHPF functions is 96kHz.

Sample rate conversion is required when routing the EQ signal paths to any signal chain that is

asynchronous and/or configured for a different sample rate.

The control registers associated with the EQ functions are described in Table 11.

The cut-off or centre frequencies for the 5-band EQ are set using the coefficients held in the registers

identified in Table 10. These coefficients are derived using tools provided in Cirrus Logic

’s WISCE™

evaluation board control software; please contact your local Cirrus Logic representative for more

details.

EQ1

R3602 (0E10h) to R3620 (0E24h)

EQ2

R3624 (0E28h) to R3642 (0E3Ah)

EQ3

R3646 (0E3Eh) to R3664 (0E53h)

EQ4

R3668 (0E54h) to R3686 (0E66h)

Table 10 EQ Coefficient Registers

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3585

(0E01h)

FX_Ctrl2

15:4

FX_STS [11:0]

00h

LHPF, DRC, EQ Enable Status

Indicates the status of each of the

respective signal processing functions.

[11] = EQ4

[10] = EQ3

[9] = EQ2

[8] = EQ1

[7] = DRC2 (Right)

[6] = DRC2 (Left)

[5] = DRC1 (Right)

[4] = DRC1 (Left)

[3] = LHPF4

[2] = LHPF3

[1] = LHPF2

[0] = LHPF1

Each bit is coded as:

0 = Disabled

1 = Enabled

R3600

(0E10h)

EQ1_1

15:11

EQ1_B1_GAIN

[4:0]

01100

EQ1 Band 1 Gain

-12dB to +12dB in 1dB steps

(see Table 12 for gain range)

10:6

EQ1_B2_GAIN

[4:0]

01100

EQ1 Band 2 Gain

-12dB to +12dB in 1dB steps

(see Table 12 for gain range)

WM8281ECS/R Scheda tecnica(PDF) 73 Page - Cirrus Logic

WM8281ECS/R Scheda tecnica(HTML) 73 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL