WM8281ECSSLASHR datasheet(35/392 Pages) CIRRUS

Il numero della parte	WM8281ECS/R

Spiegazioni elettronici	Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation

PDF	392 Pages

Scroll/Zoom	100%

Produttore elettronici	CIRRUS [Cirrus Logic]

Homepage	http://www.cirrus.com

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WM8281

Rev 4.0

DIGITAL AUDIO INTERFACE - MASTER MODE

BCLK

(output)

LRCLK

(output)

TXDAT

(output)

RXDAT

(input)

tDD

tDH

tDSU

tLRD

tBCH

tBCL

tBCY

Figure 5 Audio Interface Timing - Master Mode

Note that BCLK and LRCLK outputs can be inverted if required; Figure 5 shows the default, non-

inverted polarity.

Test Conditions

The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted.

CLOAD = 15pF to 25pF (output pins). BCLK slew (10% to 90%) = 3.7ns to 5.6ns.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Interface Timing - Master Mode

AIFnBCLK cycle time

tBCY

AIFnBCLK pulse width high

tBCH

AIFnBCLK pulse width low

tBCL

AIFn[TX/RX]LRCLK propagation delay from BCLK falling edge

tLRD

8.3

AIFnTXDAT propagation delay from BCLK falling edge

tDD

AIFnRXDAT setup time to BCLK rising edge

tDSU

9.2

AIFnRXDAT hold time from BCLK rising edge

tDH

Audio Interface Timing - Master Mode, Slave LRCLK

AIFnLRCLK setup time to BCLK rising edge

tLRSU

AIFnLRCLK hold time from BCLK rising edge

tLRH

Note:

The descriptions above assume non-inverted polarity of AIFnBCLK.

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