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WM8281ECS/R Scheda tecnica(PDF) 5 Page - Cirrus Logic

Il numero della parte WM8281ECS/R
Spiegazioni elettronici  Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation
PDF  392 Pages
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Produttore elettronici  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8281ECS/R Scheda tecnica(HTML) 5 Page - Cirrus Logic

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WM8281
Rev 4.0
5
OUTPUT SIGNAL PATH NOISE GATE CONTROL....................................................................................................................196
OUTPUT SIGNAL PATH AEC LOOPBACK ................................................................................................................................198
HEADPHONE OUTPUTS AND MONO MODE ...........................................................................................................................199
SPEAKER OUTPUTS (ANALOGUE) ..........................................................................................................................................200
SPEAKER OUTPUTS (DIGITAL PDM) .......................................................................................................................................201
EXTERNAL ACCESSORY DETECTION ...............................................................................204
JACK DETECT ............................................................................................................................................................................204
JACK POP SUPPRESSION (MICDET CLAMP AND GP SWITCH) ...........................................................................................206
MICROPHONE DETECT.............................................................................................................................................................208
HEADPHONE DETECT...............................................................................................................................................................214
LOW POWER SLEEP CONFIGURATION .............................................................................220
SLEEP MODE..............................................................................................................................................................................220
SLEEP CONTROL SIGNALS - JD1, GP5, MICDET CLAMP ......................................................................................................223
WAKE-UP TRANSITION .............................................................................................................................................................224
WRITE SEQUENCE CONTROL..................................................................................................................................................225
INTERRUPT CONTROL..............................................................................................................................................................226
GENERAL PURPOSE INPUT / OUTPUT ..............................................................................227
GPIO CONTROL .........................................................................................................................................................................228
GPIO FUNCTION SELECT .........................................................................................................................................................230
DIGITAL AUDIO INTERFACE FUNCTION (AIFNTXLRCLK)......................................................................................................235
BUTTON DETECT (GPIO INPUT) ..............................................................................................................................................235
LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT (GPIO OUTPUT)................................................................................................................235
INTERRUPT (IRQ) STATUS OUTPUT .......................................................................................................................................235
DSP STATUS FLAG (DSP IRQN) OUTPUT ...............................................................................................................................236
OPCLK AND OPCLK_ASYNC CLOCK OUTPUT .......................................................................................................................236
FREQUENCY LOCKED LOOP (FLL) STATUS OUTPUT ...........................................................................................................238
FREQUENCY LOCKED LOOP (FLL) CLOCK OUTPUT.............................................................................................................238
PULSE WIDTH MODULATION (PWM) SIGNAL OUTPUT .........................................................................................................239
HEADPHONE DETECTION STATUS OUTPUT .........................................................................................................................239
MICROPHONE / ACCESSORY DETECTION STATUS OUTPUT..............................................................................................239
HEADPHONE ENABLE STATUS OUTPUT ................................................................................................................................239
BOOT DONE STATUS OUTPUT ................................................................................................................................................240
ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) LOCK STATUS OUTPUT .............................................................240
ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) CONFIGURATION ERROR STATUS OUTPUT...........................240
ISOCHRONOUS SAMPLE RATE CONVERTER (ISRC) CONFIGURATION ERROR STATUS OUTPUT................................241
OVER-TEMPERATURE, SHORT CIRCUIT PROTECTION, AND SPEAKER SHUTDOWN STATUS OUTPUT.......................241
DYNAMIC RANGE CONTROL (DRC) STATUS OUTPUT..........................................................................................................242
CONTROL WRITE SEQUENCER STATUS OUTPUT ................................................................................................................242
CONTROL INTERFACE ERROR STATUS OUTPUT .................................................................................................................243
SYSTEM CLOCKS ENABLE STATUS OUTPUT ........................................................................................................................243
CLOCKING ERROR STATUS OUTPUT .....................................................................................................................................244
GENERAL PURPOSE SWITCH ..................................................................................................................................................245
INTERRUPTS ........................................................................................................................246
CLOCKING AND SAMPLE RATES .......................................................................................262
SYSTEM CLOCKING ..................................................................................................................................................................262
SAMPLE RATE CONTROL .........................................................................................................................................................262
AUTOMATIC SAMPLE RATE DETECTION................................................................................................................................263
SYSCLK AND ASYNCCLK CONTROL .......................................................................................................................................264
MISCELLANEOUS CLOCK CONTROLS ....................................................................................................................................267
BCLK AND LRCLK CONTROL....................................................................................................................................................274
CONTROL INTERFACE CLOCKING ..........................................................................................................................................274
FREQUENCY LOCKED LOOP (FLL) ..........................................................................................................................................275
FREE-RUNNING FLL MODE ......................................................................................................................................................285
SPREAD SPECTRUM FLL CONTROL .......................................................................................................................................287
FLL INTERRUPTS AND GPIO OUTPUT ....................................................................................................................................288



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