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WM8281ECS/R Scheda tecnica(PDF) 88 Page - Cirrus Logic |
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WM8281ECS/R Scheda tecnica(HTML) 88 Page - Cirrus Logic |
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88 / 392 page ![]() WM8281 88 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2:0 DRC2_LO_COM P [2:0] 000 DRC2 Compressor slope (lower region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 = Reserved 11X = Reserved R3724 (0E8Ch) DRC2 ctrl4 10:5 DRC2_KNEE_IP [5:0] 000000 DRC2 Input signal level at the Compressor ‘Knee’. 000000 = 0dB 000001 = -0.75dB 000010 = -1.5dB … (-0.75dB steps) 111100 = -45dB 111101 = Reserved 11111X = Reserved 4:0 DRC2_KNEE_O P [4:0] 00000 DRC2 Output signal at the Compressor ‘Knee’. 00000 = 0dB 00001 = -0.75dB 00010 = -1.5dB … (-0.75dB steps) 11110 = -22.5dB 11111 = Reserved R3725 (0E8Dh) DRC2 ctrl5 9:5 DRC2_KNEE2_I P [4:0] 00000 DRC2 Input signal level at the Noise Gate threshold ‘Knee2’. 00000 = -36dB 00001 = -37.5dB 00010 = -39dB … (-1.5dB steps) 11110 = -81dB 11111 = -82.5dB Only applicable when DRC2_NG_ENA = 1. 4:0 DRC2_KNEE2_ OP [4:0] 00000 DRC2 Output signal at the Noise Gate threshold ‘Knee2’. 00000 = -30dB 00001 = -31.5dB 00010 = -33dB … (-1.5dB steps) 11110 = -75dB 11111 = -76.5dB Only applicable when DRC2_KNEE2_OP_ENA = 1. Table 16 DRC2 Control Registers |
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