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WM8281ECS/R Scheda tecnica(PDF) 8 Page - Cirrus Logic |
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WM8281ECS/R Scheda tecnica(HTML) 8 Page - Cirrus Logic |
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8 / 392 page ![]() WM8281 8 Rev 4.0 ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM8281ECS/R -40 C to +85C W-CSP (Pb-free, Tape and reel) MSL1 260 C Note: Reel quantity = 7000 PIN DESCRIPTION A description of each pin on the WM8281 is provided below. Note that a table detailing the associated power domain for every input and output pin is provided on the following page. Note that, where multiple pins share a common name, these pins should be tied together on the PCB. All Digital Output pins are CMOS outputs, unless otherwise stated. PIN NO NAME TYPE DESCRIPTION E2 AGND1 Supply Analogue ground (Return path for AVDD1) D13 AGND2 Supply Analogue ground (Return path for AVDD2) J13 AIF1BCLK Digital Input / Output Audio interface 1 bit clock H13 AIF1RXDAT Digital Input Audio interface 1 RX digital audio data H12 AIF1LRCLK Digital Input / Output Audio interface 1 left / right clock J11 AIF1TXDAT Digital Output Audio interface 1 TX digital audio data K9 AIF2BCLK Digital Input / Output Audio interface 2 bit clock J8 AIF2RXDAT Digital Input Audio interface 2 RX digital audio data J9 AIF2LRCLK Digital Input / Output Audio interface 2 left / right clock K8 AIF2TXDAT Digital Output Audio interface 2 TX digital audio data K7 AIF3BCLK Digital Input / Output Audio interface 3 bit clock H4 AIF3RXDAT Digital Input Audio interface 3 RXdigital audio data J7 AIF3LRCLK Digital Input / Output Audio interface 3 left / right clock H5 AIF3TXDAT Digital Output Audio interface 3 TX digital audio data E1 AVDD1 Supply Analogue supply C14 AVDD2 Supply Analogue supply F12 CIF1ADDR/ CIF1SS ¯¯¯¯¯¯ Digital Input Control interface 1 (I2C) address select / Control interface 1 (SPI) Slave Select (SS) J12 CIF1MISO/ GPIO4 Digital Input / Output Control interface 1 Master In Slave Out data / General Purpose pin GPIO4. The CIFMISO configuration is selectable CMOS or ‘Wired OR’. The GPIO4 output is selectable CMOS or Open Drain. F11 CIF1MODE Digital Input Control interface 1 mode select input G13 CIF1SCLK Digital Input Control interface 1 clock input G12 CIF1SDA/ CIF1MOSI Digital Input / Output Control interface 1 (I2C) data input and output / Control interface 1 (SPI) Master Out Slave In data. The output functions are implemented as an Open Drain circuit. L12 CIF2SCLK Digital Input Control interface 2 clock input K10 CIF2SDA Digital Input / Output Control interface 2 data input and output / acknowledge output. The output function is implemented as an Open Drain circuit. C5 CP1C1A Analogue Output Charge pump 1 fly-back capacitor 1 pin C6 CP1C1B Analogue Output Charge pump 1 fly-back capacitor 1 pin B6 CP1C2A Analogue Output Charge pump 1 fly-back capacitor 2 pin A6 CP1C2B Analogue Output Charge pump 1 fly-back capacitor 2 pin C7 CP1VOUT1N Analogue Output Charge pump 1 negative output 1 decoupling pin B8 CP1VOUT1P Analogue Output Charge pump 1 positive output 1 decoupling pin A7 CP1VOUT2N Analogue Output Charge pump 1 negative output 2 decoupling pin |
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