WM8281ECSSLASHR datasheet(89/392 Pages) CIRRUS

89 / 392 page

WM8281

Rev 4.0

The WM8281 performs automatic checks to confirm that the SYSCLK frequency is high enough to

support the commanded DRC and digital mixing functions. If an attempt is made to enable a DRC

signal path, and there are insufficient SYSCLK cycles to support it, then the attempt will be

unsuccessful. (Note that any signal paths that are already active will not be affected under these

circumstances.)

The Underclocked Error

can be monitored using the GPIO and/or Interrupt functions. See “General

Purpose Input / Output

” and “Interrupts” for further details.

The FX_STS field in Register R3585 indicates the status of each of the EQ, DRC and LHPF signal

paths. If an Underclocked Error condition occurs, then this register provides readback of which EQ,

DRC or LHPF signal path(s) have been successfully enabled.

The status bits in Registers R1600 to R3000 indicate the status of each of the digital mixers. If an

Underclocked Error condition occurs, then these bits provide readback of which mixer(s) have been

successfully enabled.

LOW PASS / HIGH PASS DIGITAL FILTER (LHPF)

The digital core provides four Low Pass Filter (LPF) / High Pass Filter (HPF) processing blocks as

illustrated in Figure 32. A 4-input mixer is associated with each filter. The 4 input sources are

selectable in each case, and independent volume control is provided for each path. Each Low/High

Pass Filter (LHPF) block supports 1 output.

The Low Pass Filter / High Pass Filter can be used to remove unwanted out-of-band noise from a

signal path. Each filter can be configured either as a Low Pass filter or High Pass filter.

WM8281 supports 4 LHPF blocks, ie. n = 1, 2, 3 or 4

LHPFnMIX_VOL2

LHPFnMIX_VOL3

LHPFnMIX_VOL4

LHPFnMIX_VOL1

LHPFnMIX_SRC1

LHPFnMIX_SRC3

LHPFnMIX_SRC4

LHPFnMIX_SRC2

LHPF1 (60h)

LHPF2 (61h)

LHPF3 (62h)

LHPF4 (63h)

LHPF

Low-Pass filter (LPF) /

High-Pass filter (HPF)

Figure 32 Digital Core LPF/HPF Blocks

The LHPF1, LHPF2, LHPF3 and LHPF4 mixer control registers (see Figure 32) are located at register

addresses R2304 (900h) through to R2335 (91Fh).

The full list of digital mixer control registers is provided in the “Register Map” section (Register R1600

through to R3000). Generic register definitions are provided in Table 8.

The *_SRCn registers select the input source(s) for the respective LHPF processing blocks. Note that

the selected input source(s) must be configured for the same sample rate as the LHPF to which they

are connected. Sample rate conversion functions are available to support flexible interconnectivity -

see “Asynchronous Sample Rate Converter (ASRC)” and “Isochronous Sample Rate Converter

(ISRC)

”.

The bracketed numbers in Figure 32

, eg. “(60h)” indicate the corresponding *_SRCn register setting

for selection of that signal as an input to another digital core function.

The sample rate for the LHPF function is configured using the FX_RATE register - see Table 23. Note

that the EQ, DRC and LHPF functions must all be configured for the same sample rate.

The LHPF function supports audio sample rates in the range 8kHz to 192kHz. When the DRC is

enabled, the maximum sample rate for the EQ, DRC and LHPF functions is 96kHz.

Sample rate conversion is required when routing the LHPF signal paths to any signal chain that is

asynchronous and/or configured for a different sample rate.

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