WM8281ECSSLASHR datasheet(10/392 Pages) CIRRUS

10 / 392 page

WM8281

Rev 4.0

PIN NO

NAME

TYPE

DESCRIPTION

IN3LN/

DMICCLK3

Analogue Input /

Digital Output

Left channel negative differential Mic/Line input /

Digital MIC clock output 3

IN3LP

Analogue Input

Left channel single-ended Mic/Line input /

Left channel positive differential Mic/Line input

IN3RN/

DMICDAT3

Analogue input /

Digital Input

Right channel negative differential Mic/Line input /

Digital MIC data input 3

IN3RP

Analogue Input

Right channel single-ended Mic/Line input /

Right channel positive differential Mic/Line input

E11

IRQ

¯¯¯

Digital Output

Interrupt Request (IRQ) output (default is active low).

The pin configuration is selectable CMOS or Open Drain.

C13

JACKDET

Analogue Input

Jack detect input

E13

LDOENA

Digital Input

Enable pin for LDO1 (generates DCVDD supply).

Logic 1 input enables LDO1. If using external DCVDD supply,

then LDO1 is not used, and LDOENA must be held at logic 0.

F14

LDOVDD

Supply

Supply for LDO1

E14

LDOVOUT

Analogue Output

LDO1 output.

If using external DCVDD, then LDOVOUT must be left floating.

K13

MCLK1

Digital Input

Master clock 1

G14

MCLK2

Digital Input

Master clock 2

MICBIAS1

Analogue Output

Microphone bias 1

MICBIAS2

Analogue Output

Microphone bias 2

MICBIAS3

Analogue Output

Microphone bias 3

A14

MICDET1/

HPOUT1FB2

Analogue Input

Microphone & accessory sense input 1/

HPOUT1L and HPOUT1R ground feedback pin 2

MICVDD

Analogue Output

LDO2 output decoupling pin (generated internally by WM8281).

(Can also be used as reference/supply for external

microphones.)

E12

RESET

¯¯¯¯¯¯

Digital Input

Digital Reset input (active low)

L13

SLIMCLK

Digital Input / Output

SLIM Bus Clock input / output

K12

SLIMDAT

Digital Input / Output

SLIM Bus Data input / output

SPKCLK1

Digital Output

Digital speaker (PDM) 1 clock output

SPKCLK2

Digital Output

Digital speaker (PDM) 2 clock output

H10

SPKDAT1

Digital Output

Digital speaker (PDM) 1 data output

SPKDAT2

Digital Output

Digital speaker (PDM) 2 data output

SPKGNDLN

Supply

Left speaker driver ground (Return path for SPKVDDL).

See note.

SPKGNDLP

Supply

Left speaker driver ground (Return path for SPKVDDL).

See note.

SPKGNDRN

Supply

Right speaker driver ground (Return path for SPKVDDR).

See note.

SPKGNDRP

Supply

Right speaker driver ground (Return path for SPKVDDR).

See note.

SPKOUTLN

Analogue Output

Left speaker negative output

SPKOUTLP

Analogue Output

Left speaker positive output

SPKOUTRN

Analogue Output

Right speaker negative output

SPKOUTRP

Analogue Output

Right speaker positive output

SPKTST1

Analogue Output

Test function (recommend no external connection)

SPKTST2

Analogue Output

Test function (recommend no external connection)

K6, L6

SPKVDDL

Supply

Left speaker driver supply

K1, L1

SPKVDDR

Supply

Right speaker driver supply

D14, F2

SUBGND

Supply

Substrate ground

TCK

Digital Input

JTAG clock input.

Internal pull-down holds this pin at logic 0 for normal operation.

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