WM8281ECSSLASHR datasheet(92/392 Pages) CIRRUS

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WM8281

Rev 4.0

DIGITAL CORE DSP

The digital core provides four programmable DSP processing blocks as illustrated in Figure 33. Each

block supports 8 inputs (Left, Right, Aux1, Aux2, … Aux6). A 4-input mixer is associated with the Left

and Right inputs, providing further expansion of the number of input paths. Each of the input sources

is selectable, and independent volume control is provided for Left and Right input mixer channels.

Each DSP block supports 6 outputs.

The functionality of the DSP processing blocks is not fixed, and a wide range of audio enhancements

algorithms may be performed. The procedure for configuring the WM8281 DSP functions is tailored to

each customer’s application; please contact your local Cirrus Logic representative for more details.

For details of the DSP Firmware requirements relating to clocking, register access, and code

execution, refer to the “DSP Firmware Control” section.

DSPnLMIX_VOL2

DSPnLMIX_VOL3

DSPnLMIX_VOL4

DSPnLMIX_VOL1

DSPnLMIX_SRC1

DSPnLMIX_SRC3

DSPnLMIX_SRC4

DSPnLMIX_SRC2

DSPnRMIX_VOL2

DSPnRMIX_VOL3

DSPnRMIX_VOL4

DSPnRMIX_VOL1

DSPnRMIX_SRC1

DSPnRMIX_SRC3

DSPnRMIX_SRC4

DSPnRMIX_SRC2

DSP n

DSPn Channel 1

DSPn Channel 2

DSPn Channel 3

DSPn Channel 4

DSPn Channel 5

DSPn Channel 6

WM8281 supports 4 DSP blocks, ie. n = 1, 2, 3 or 4

DSP1 Outputs:

(68h, 69h, 6Ah,

6Bh, 6Ch, 6Dh)

DSP2 Outputs:

(70h, 71h, 72h,

73h, 74h, 75h)

DSP3 Outputs:

(78h, 79h, 7Ah,

7Bh, 7Ch, 7Dh)

DSP4 Outputs:

(80h, 81h, 82h,

83h, 84h, 85h)

Figure 33 Digital Core DSP Blocks

The DSP1, DSP2, DSP 3 and DSP4 mixer / input control registers (see Figure 33) are located at

The full list of digital mixer control registers is provided in the

“Register Map” section (Register R1600

through to R3000). Generic register definitions are provided in Table 8.

The *_SRCn registers select the input source(s) for the respective DSP processing blocks. Note that

the selected input source(s) must be configured for the same sample rate as the DSP to which they

are connected. Sample rate conversion functions are available to support flexible interconnectivity -

see “Asynchronous Sample Rate Converter (ASRC)” and “Isochronous Sample Rate Converter

(ISRC)

”.

The bracketed numbers in Figure 33, eg

. “(68h)” indicate the corresponding *_SRCn register setting

for selection of that signal as an input to another digital core function.

The sample rate for each of the DSP functions is configured using the respective DSPn_RATE

registers - see Table 23. Sample rate conversion is required when routing the DSPn signal paths to

any signal chain that is asynchronous and/or configured for a different sample rate.

The WM8281 performs automatic checks to confirm that the SYSCLK frequency is high enough to

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