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WM8281ECS/R Scheda tecnica(PDF) 53 Page - Cirrus Logic

Il numero della parte WM8281ECS/R
Spiegazioni elettronici  Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation
PDF  392 Pages
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Produttore elettronici  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8281ECS/R Scheda tecnica(HTML) 53 Page - Cirrus Logic

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WM8281
Rev 4.0
53
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Control
7:1
IN1R_PGA_VOL
[6:0]
40h
Input Path 1 (Right) PGA Volume
(Applicable to analogue inputs only)
00h to 3Fh = Reserved
40h = 0dB
41h = 1dB
42h = 2dB
… (1dB steps)
5F = 31dB
60h to 7Fh = Reserved
R790
(0316h)
DMIC1R
Control
5:0
IN1R_DMIC_DLY
[5:0]
00h
Input Path 1 (Right) Digital Delay
(Applicable to digital input only)
LSB = 1 sample, Range is 0 to 63.
(Sample rate is controlled by IN1_OSR.)
R792
(0318h)
IN2L
Control
15
IN2L_HPF
0
Input Path 2 (Left) HPF Enable
0 = Disabled
1 = Enabled
14:13
IN2_OSR [1:0]
01
Input Path 2 DMIC Oversample Rate
When digital microphone input is selected
(IN2_MODE=10), this field controls the
sample rate as below:
00 = 1.536MHz
01 = 3.072MHz
10 = 6.144MHz
11 = 768kHz
When IN2_OSR=11, the Input Path
sample rate (for all input paths) must be in
the range 8kHz to 16kHz.
If Input Path 2 DMIC is selected as a
source for the Rx ANC function, the
DMICCLK2 frequency will be set to
3.072MHz.
12:11
IN2_DMIC_SUP
[1:0]
00
Input Path 2 DMIC Reference Select
(Sets the DMICDAT2 and DMICCLK2
logic levels)
00 = MICVDD
01 = MICBIAS1
10 = MICBIAS2
11 = MICBIAS3
10:9
IN2_MODE [1:0]
00
Input Path 2 Mode
00 = Differential (IN2xP - IN2xN)
01 = Single-ended (IN2xP)
10 = Digital Microphone
11 = Reserved
7:1
IN2L_PGA_VOL
[6:0]
40h
Input Path 2 (Left) PGA Volume
(Applicable to analogue inputs only)
00h to 3Fh = Reserved
40h = 0dB
41h = 1dB
42h = 2dB
… (1dB steps)
5F = 31dB
60h to 7Fh = Reserved
R794
(031Ah)
DMIC2L
Control
5:0
IN2L_DMIC_DLY
[5:0]
00h
Input Path 2 (Left) Digital Delay
(Applicable to digital input only)
LSB = 1 sample, Range is 0 to 63.
(Sample rate is controlled by IN2_OSR.)



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