WM8281ECSSLASHR datasheet(80/392 Pages) CIRRUS

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WM8281

Rev 4.0

Dynamic Characteristics

The dynamic behaviour determines how quickly the DRC responds to changing signal levels. Note

that the DRC responds to the average (RMS) signal amplitude over a period of time.

The DRCn_ATK determines how quickly the DRC gain decreases when the signal amplitude is high.

The DRCn_DCY determines how quickly the DRC gain increases when the signal amplitude is low.

These register fields are described in Table 15. Note that the register defaults are suitable for general

purpose microphone use.

Anti-Clip Control

The DRC includes an Anti-Clip feature to avoid signal clipping when the input amplitude rises very

quickly. This feature uses a feed-forward technique for early detection of a rising signal level. Signal

clipping is avoided by dynamically increasing the gain attack rate when required. The Anti-Clip feature

is enabled using the DRCn_ANTICLIP bit.

Note that the feed-forward processing increases the latency in the input signal path.

Note that the Anti-Clip feature operates entirely in the digital domain. It cannot be used to prevent

signal clipping in the analogue domain nor in the source signal. Analogue clipping can only be

prevented by reducing the analogue signal gain or by adjusting the source signal.

Quick Release Control

The DRC includes a Quick-Release feature to handle short transient peaks that are not related to the

intended source signal. For example, in handheld microphone recording, transient signal peaks

sometimes occur due to user handling, key presses or accidental tapping against the microphone.

The Quick Release feature ensures that these transients do not cause the intended signal to be

masked by the longer time constant of DRCn_DCY.

The Quick-Release feature is enabled by setting the DRCn_QR bit. When this bit is enabled, the DRC

measures the crest factor (peak to RMS ratio) of the input signal. A high crest factor is indicative of a

transient peak that may not be related to the intended source signal. If the crest factor exceeds the

level set by DRCn_QR_THR, then the normal decay rate (DRCn_DCY) is ignored and a faster decay

rate (DRCn_QR_DCY) is used instead.

Signal Activity Detect

The DRC incorporates a configurable signal detect function, allowing the signal level at the DRC input

to be monitored and to be used to trigger other events. This can be used to detect the presence of a

microphone signal on an ADC or digital mic channel, or can be used to detect an audio signal

received over the digital audio interface.

The DRC Signal Detect function is enabled by setting DRCn_SIG_DET register bit. (Note that the

respective DRCn must also be enabled.) The detection threshold is either a Peak level (Crest Factor)

or an RMS level, depending on the DRCn_SIG_DET_MODE register bit. When Peak level is selected,

the threshold is determined by DRCn_SIG_DET_PK, which defines the applicable Crest Factor (Peak

RMS

ratio)

threshold.

RMS

level

selected,

then

the

threshold

set

using

DRCn_SIG_DET_RMS.

The DRC Signal Detect function is an input to the Interrupt control circuit and can be used to trigger

an Interrupt event -

see “Interrupts”.

The DRC Signal Detect signal can be output directly on a GPIO pin as an external indication of the

Signal Detection

. See “General Purpose Input / Output” to configure a GPIO pin for this function.

The Control Write Sequencer can be triggered by the DRC1 Signal Detect function. This is enabled

using the DRC1_WSEQ_SIG_DET_ENA register bit. See “Control Write Sequencer” for further

details.

Note that signal detection is supported on DRC1 and DRC2, but the triggering of the Control Write

Sequencer is available on DRC1 only.

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