WM8281ECSSLASHR datasheet(36/392 Pages) CIRRUS

36 / 392 page

WM8281

Rev 4.0

DIGITAL AUDIO INTERFACE - SLAVE MODE

BCLK

(input)

LRCLK

(input)

TXDAT

(output)

RXDAT

(input)

tDSU

tDD

tDH

tLRH

tLRSU

tBCH

tBCL

tBCY

Figure 6 Audio Interface Timing - Slave Mode

Note that BCLK and LRCLK inputs can be inverted if required; Figure 6 shows the default, non-

inverted polarity.

Test Conditions

The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Interface Timing - Slave Mode

AIFnBCLK cycle time

tBCY

AIFnBCLK pulse width high

BCLK as direct SYSCLK or

ASYNCCLK source

tBCH

All other conditions

AIFnBCLK pulse width low

BCLK as direct SYSCLK or

ASYNCCLK source

tBCL

All other conditions

Audio Interface Timing - Slave Mode

CLOAD = 15pF (output pins). BCLK slew (10% to 90%) = 3ns.

AIFn[TX/RX]LRCLK set-up time to BCLK rising edge

tLRSU

AIFn[TX/RX]LRCLK hold time from BCLK rising edge

tLRH

AIFnTXDAT propagation delay from BCLK falling edge

tDD

10.7

AIFnRXDAT set-up time to BCLK rising edge

tDSU

AIFnRXDAT hold time from BCLK rising edge

tDH

Audio Interface Timing - Slave Mode

CLOAD = 25pF (output pins). BCLK slew (10% to 90%) = 6ns.

AIFn[TX/RX]LRCLK set-up time to BCLK rising edge

tLRSU

AIFn[TX/RX]LRCLK hold time from BCLK rising edge

tLRH

AIFnTXDAT propagation delay from BCLK falling edge

tDD

12.7

AIFnRXDAT set-up time to BCLK rising edge

tDSU

AIFnRXDAT hold time from BCLK rising edge

tDH

Audio Interface Timing - Slave Mode, Master LRCLK

AIFn[TX/RX]LRCLK propagation delay from BCLK falling edge

CLOAD = 15pF (output pins). BCLK slew (10% to 90%) = 3ns.

tLRD

14.8

AIFn[TX/RX]LRCLK propagation delay from BCLK falling edge

CLOAD = 25pF (output pins). BCLK slew (10% to 90%) = 6ns.

15.9

Notes:

The descriptions above assume non-inverted polarity of AIFnBCLK.

When AIFnBCLK or AIFnLRCLK is selected as a source for SYSCLK or ASYNCCLK (either directly or via one of the FLLs), the

frequency must be within 1% of the applicable SYSCLK_FREQ or ASYNCCLK_FREQ register setting.

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