WM8281ECSSLASHR datasheet(50/392 Pages) CIRRUS

50 / 392 page

WM8281

Rev 4.0

INPUT SIGNAL PATH ENABLE

The input signal paths are enabled using the register bits described in Table 2. The respective bit(s)

must be enabled for analogue or digital input on the respective input path(s).

The input signal paths are muted by default. It is recommended that de-selecting the mute should be

the final step of the path enable control sequence. Similarly, the mute should be selected as the first

step of the path disable control sequence. The input signal path mute functions are controlled using

the register bits described in Table 4.

The MICVDD power domain must be enabled when using the analogue input signal path(s). This

power domain is provided using an internal Charge Pump (CP2) and LDO Regulator (LDO2). See

“Charge Pumps, Regulators and Voltage Reference” for details of these circuits.

The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. The

ASYNCCLK and 32kHz clock may also be required, depending on the path configuration. See

“Clocking and Sample Rates” for details of the system clocks.

The WM8281 performs automatic checks to confirm that the SYSCLK frequency is high enough to

support the input signal paths and associated ADCs. If an attempt is made to enable an input signal

path, and there are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful.

(Note that any signal paths that are already active will not be affected under these circumstances.)

The Underclocked Error condition can be monitored using the GPIO and/or Interrupt functions. See

“General Purpose Input / Output” and “Interrupts” for further details.

The status bits in Register R769 indicate the status of each of the input signal paths. If an

Underclocked Error condition occurs, then these bits provide readback of which input signal path(s)

have been successfully enabled.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R768

(0300h)

Input

Enables

IN4L_ENA

Input Path 4 (Left) Enable

0 = Disabled

1 = Enabled

IN4R_ENA

Input Path 4 (Right) Enable

0 = Disabled

1 = Enabled

IN3L_ENA

Input Path 3 (Left) Enable

0 = Disabled

1 = Enabled

IN3R_ENA

Input Path 3 (Right) Enable

0 = Disabled

1 = Enabled

IN2L_ENA

Input Path 2 (Left) Enable

0 = Disabled

1 = Enabled

IN2R_ENA

Input Path 2 (Right) Enable

0 = Disabled

1 = Enabled

IN1L_ENA

Input Path 1 (Left) Enable

0 = Disabled

1 = Enabled

IN1R_ENA

Input Path 1 (Right) Enable

0 = Disabled

1 = Enabled

R769

(0301h)

Input

Enables

Status

IN4L_ENA_STS

Input Path 4 (Left) Enable Status

0 = Disabled

1 = Enabled

IN4R_ENA_STS

Input Path 4 (Right) Enable Status

0 = Disabled

1 = Enabled

IN3L_ENA_STS

Input Path 3 (Left) Enable Status

0 = Disabled

1 = Enabled

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