WM8281ECSSLASHR datasheet(85/392 Pages) CIRRUS

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WM8281

Rev 4.0

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

4:0

DRC1_KNEE2_

OP [4:0]

00000

DRC1 Output signal at the Noise

Gate threshold ‘Knee2’.

00000 = -30dB

00001 = -31.5dB

00010 = -33dB

… (-1.5dB steps)

11110 = -75dB

11111 = -76.5dB

Only applicable when

DRC1_KNEE2_OP_ENA = 1.

Table 15 DRC1 Control Registers

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3585

(0E01h)

FX_Ctrl2

15:4

FX_STS [11:0]

00h

LHPF, DRC, EQ Enable Status

Indicates the status of each of the

respective signal processing

functions.

[11] = EQ4

[10] = EQ3

[9] = EQ2

[8] = EQ1

[7] = DRC2 (Right)

[6] = DRC2 (Left)

[5] = DRC1 (Right)

[4] = DRC1 (Left)

[3] = LHPF4

[2] = LHPF3

[1] = LHPF2

[0] = LHPF1

Each bit is coded as:

0 = Disabled

1 = Enabled

R3721

(0E89h)

DRC2 ctrl1

15:11

DRC2_SIG_DET

_RMS [4:0]

00h

DRC2 Signal Detect RMS

Threshold.

This is the RMS signal level for

signal detect to be indicated when

DRC2_SIG_DET_MODE=1.

00h = -30dB

01h = -31.5dB

…. (1.5dB steps)

1Eh = -75dB

1Fh = -76.5dB

10:9

DRC2_SIG_DET

_PK [1:0]

DRC2 Signal Detect Peak

Threshold.

This is the Peak/RMS ratio, or Crest

Factor, level for signal detect to be

indicated when

DRC2_SIG_DET_MODE=0.

00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB

DRC2_NG_ENA

DRC2 Noise Gate Enable

0 = Disabled

1 = Enabled

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