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WM8281ECS/R Scheda tecnica(PDF) 26 Page - Cirrus Logic

Il numero della parte WM8281ECS/R
Spiegazioni elettronici  Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation
PDF  392 Pages
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Produttore elettronici  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8281ECS/R Scheda tecnica(HTML) 26 Page - Cirrus Logic

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WM8281
26
Rev 4.0
Test Conditions
DBVDD1 = DBVDD2 = DBVDD3 = CPVDD = AVDD = 1.8V,
DCVDD = 1.2V (powered from LDO1), MICVDD = 2.5V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V,
TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MICVDD Charge Pump and Regulator (CP2 and LDO2)
Output voltage
VMICVDD
0.9
2.7
3.3
V
Programmable output voltage step
size
LDO2_VSEL=00h to 14h
(0.9V to 1.4V)
25
mV
LDO2_VSEL=14h to 27h
(1.4V to 3.3V)
100
Maximum output current
8
mA
Start-up time
4.7µF on MICVDD
1.5
2.5
ms
Frequency Locked Loop (FLL1, FLL2)
Output frequency
39
156
MHz
Lock Time
FREF = 32kHz,
FOUT = 147.456MHz
10
ms
FREF = 12MHz,
FOUT = 147.456MHz
1
RESET pin Input
RESET input pulse width
(To trigger a Hardware Reset, the
RESET input must be asserted for
longer than this duration)
1
µs
Test Conditions
The following electrical characteristics are valid across the full range of recommended operating conditions.
Device Reset Thresholds
AVDD Reset Threshold
VAVDD
VAVDD rising
1.56
V
VAVDD falling
0.92
1.55
DCVDD Reset Threshold
VDCVDD
VDCVDD rising
1.04
V
VDCVDD falling
0.49
0.64
DBVDD1 Reset Threshold
VDBVDD1
VDBVDD1 rising
1.54
V
VDBVDD1 falling
0.58
1.52
Note that the reset thresholds are derived from simulations only, across all operational and process corners.
Device performance is not assured outside the voltage
ranges defined in the “Recommended Operating Conditions” section.
Refer to this section for the WM8281 power-up sequencing requirements.



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