WM8281ECSSLASHR datasheet(15/392 Pages) CIRRUS

15 / 392 page

WM8281

Rev 4.0

RECOMMENDED OPERATING CONDITIONS

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Digital supply range (Core)

See notes 2, 3, 4

DCVDD

1.14

1.2

1.26

Digital supply range (I/O)

See note 5

DBVDD1, DBVDD2,

DBVDD3

1.62

3.6

LDO supply range

See note 13

LDOVDD

1.71

1.8

1.89

Charge Pump supply range

CPVDD

1.71

1.8

1.89

Speaker supply range

SPKVDDL, SPKVDDR

2.4

5.5

Analogue supply range

See notes 2, 6, 7

AVDD

1.71

1.8

1.89

Microphone Bias supply

See note 8

MICVDD

0.9

2.5

3.78

Ground

See note 1

DGND, AGND, CPGND,

SPKGNDL, SPKGNDR,

SUBGND

Power supply rise time

See notes 9, 10, 11, 12

DCVDD

2000

µs

All other supplies

Operating temperature range

-40

°C

Notes:

The impedance between DGND, AGND, CPGND and SUBGND should be less than 0.1

Ω.The impedance between SPKGNDL,

SPKGNDR and SUBGND should be less than 0.2

Ω.

AVDD must be supplied before or simultaneously to DCVDD. DCVDD must not be powered if AVDD is not present. There are

no other power sequencing requirements.

An internal LDO (powered by LDOVDD) can be used to provide the DCVDD supply.

‘Sleep’ mode is supported when DCVDD is below the limits noted, provided AVDD and DBVDD1 are present.

If the SLIMbus interface is enabled, then the maximum DBVDD1 voltage is 1.98V.

The AVDD1 and AVDD2 pins should be tied together. The associated power domain is referred to as AVDD.

The AGND1 and AGND2 pins should be tied together. The associated ground domain is referred to as AGND.

An internal Charge Pump and LDO (powered by CPVDD) provide the Microphone Bias supply; the MICVDD pin should not be

connected to an external supply.

DCVDD and MICVDD minimum rise times do not apply when these domains are powered using the internal LDOs.

10. If DCVDD is supplied externally, and the rise time exceeds 2ms, then RESET

¯¯¯¯¯¯ must be asserted (low) during the rise, and held

asserted until after DCVDD is within the recommended operating limits.

11. The specified minimum power supply rise times assume a minimum decoupling capacitance of 100nF per pin. However, Cirrus

Logic strongly advises that the recommended decoupling capacitors are present on the PCB and that appropriate layout

guidelines are observed.

12. The specified minimum power supply rise times also assume a maximum PCB inductance of 10nH between decoupling

capacitor and pin.

13. When the internal LDO is used to provide the DCVDD supply, then the LDOVDD supply must be suitably rated for the inrush

current at start-up and wake-up. In the typical configuration, using the internal LDO, and with the LDOVDD / CPVDD / AVDD

domains connected to a single supply, a peak current capability of 500mA is required on this supply.

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