WM8281ECSSLASHR datasheet(40/392 Pages) CIRRUS

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WM8281

Rev 4.0

SLIMBUS INTERFACE TIMING

SLIMDAT

TDV

TCLKL

TCLKH

VIH

VIL

TSETUP

VIH, VOH

VIL, VOL

SLIMCLK

VIL, VIH are the 35%/65% levels of the respective inputs.

VOL, VOH are the 20%/80% levels of the respective outputs.

The SLIMDAT output delay (TDV) is with respect to the input pads of all receiving devices.

Figure 11 SLIMbus Interface Timing

The signal timing information shown in Figure 11 describe the timing requirements of the SLIMbus

interface as a whole, not just the WM8281 device. Accordingly, the following should be noted:



TDV is the propagation delay from the rising SLIMCLK edge (at WM8281 input) to the

SLIMDAT output being achieved at the input to all devices across the bus.



TSETUP is the set-up time for SLIMDAT input (at WM8281), relative to the falling SLIMCLK

edge (at WM8281).



TH is the hold time for SLIMDAT input (at WM8281) relative to the falling SLIMCLK edge (at

WM8281).

For more details of the interface timing, refer to the MIPI Alliance Specification for Serial Low-power

Inter-chip Media Bus (SLIMbus).

Test Conditions

The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

SLIMCLK Input

SLIMCLK cycle time

SLIMCLK pulse width high

TCLKH

SLIMCLK pulse width low

TCLKL

SLIMCLK Output

SLIMCLK cycle time

SLIMCLK pulse width high

TCLKH

SLIMCLK pulse width low

TCLKL

SLIMCLK slew rate

(20% to 80%)

CLOAD = 15pF,

SLIMCLK_DRV_STR=0

SRCLK

0.09 x

VDBVDD1

0.22 x

VDBVDD1

V/ns

CLOAD = 70pF,

SLIMCLK_DRV_STR=0

0.02 x

VDBVDD1

0.05 x

VDBVDD1

CLOAD = 70pF,

SLIMCLK_DRV_STR=1

0.04 x

VDBVDD1

0.11 x

VDBVDD1

SLIMDAT Input

SLIMDAT setup time to SLIMCLK falling edge

TSETUP

3.5

SLIMDAT hold time from SLIMCLK falling edge

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