WM8281ECSSLASHR datasheet(112/392 Pages) CIRRUS

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WM8281

112

Rev 4.0

ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC)

The WM8281 supports multiple signal paths through the digital core. Two independent clock domains

are supported, referenced to SYSCLK and ASYNCCLK respe

ctively, as described in “Clocking and

Sample Rates

”. Every digital signal path must be synchronised either to SYSCLK or to ASYNCCLK.

The Asynchronous Sample Rate Converter (ASRC) provides two stereo signal paths between the

SYSCLK and ASYNCCLK domains, as illustrated in Figure 40.

The sample rate on the SYSCLK domain is selected using the ASRC_RATE1 register - the rate can

be set equal to SAMPLE_RATE_1, SAMPLE_RATE_2 or SAMPLE_RATE_3.

The sample rate on the ASYNCCLK domain is selected using the ASRC_RATE2 register - the rate

can be set equal to ASYNC_SAMPLE_RATE_1 or ASYNC_SAMPLE_RATE_2.

See “Clocking and Sample Rates” for details of the sample rate control registers.

The ASRC_RATE1 and ASRC_RATE2 registers should not be changed if any of the respective

*_SRCn registers is non-zero. The associated *_SRCn registers should be cleared to 00h before

writing new values to ASRC_RATE1 or ASRC_RATE2. A minimum delay of 125µs should be allowed

between clearing the *_SRCn registers and writing to the associated ASRC_RATE1 or ASRC_RATE2

registers. See Table 24 for further details.

The ASRC supports sample rates in the range 8kHz to 48kHz only. The applicable SAMPLE_RATE_n

and ASYNC_SAMPLE_RATE_n registers must each select sample rates between 8kHz and 48kHz

when any ASRC path is enabled.

The ASRC1 Left and ASRC1 Right paths convert from the SYSCLK domain to the ASYNCCLK

domain. These paths are enabled using the ASRC1L_ENA and ASRC1R_ENA register bits

respectively.

The ASRC2 Left and ASRC2 Right paths convert from the ASYNCCLK domain to the SYSCLK

domain. These paths are enabled using the ASRC2L_ENA and ASRC2R_ENA register bits

respectively.

Synchronisation (lock) between different clock domains is not instantaneous when the clocking or

sample rate configurations are updated. The lock status of each ASRC path is an input to the Interrupt

control circuit and can be used to trigger an Interrupt event -

see “Interrupts”.

The ASRC Lock status of each ASRC path can be output directly on a GPIO pin as an external

indication of ASRC Lock. See “General Purpose Input / Output” to configure a GPIO pin for this

function.

The WM8281 performs automatic checks to confirm that the SYSCLK or ASYNCCLK frequency is

high enough to support the commanded ASRC and digital mixing functions. If an attempt is made to

enable an ASRC signal path, and there are insufficient SYSCLK or ASYNCLK cycles to support it,

then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be

affected under these circumstances.)

The Underclocked Error

can be monitored using the GPIO and/or Interrupt functions. See “General

Purpose Input / Output

” and “Interrupts” for further details.

The status bits in Register R3809 indicate the status of each of the ASRC signal paths. If an

Underclocked Error condition occurs, then these bits provide readback of which ASRC signal path(s)

have been successfully enabled.

The status bits in Registers R1600 to R3000 indicate the status of each of the digital mixers. If an

Underclocked Error condition occurs, then these bits provide readback of which mixer(s) have been

successfully enabled.

The Asynchronous Sample Rate Converter (ASRC) signal paths and control registers are illustrated in

Figure 40.

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