WM8281ECSSLASHR datasheet(148/392 Pages) CIRRUS

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WM8281

148

Rev 4.0

DIGITAL AUDIO INTERFACE CONTROL

This section describes the configuration of the WM8281 digital audio interface paths.

AIF1 supports up to 8 input signal paths and up to 8 output signal paths; AIF2 supports up to 6

channels of input and output signal paths; AIF3 supports up to 2 channels of input and output signal

paths. The digital audio interfaces AIF1, AIF2 and AIF3 can be configured as Master or Slave

interfaces; mixed master/slave configurations are also possible.

Each input and output signal path can be independently enabled or disabled. The AIF output (TX) and

AIF input (RX) paths can use a common LRCLK frame clock, or can use separate LRCLK signals if

required.

The digital audio interface supports flexible data formats, selectable word-length, configurable timeslot

allocations and TDM tri-state control.

AIF SAMPLE RATE CONTROL

The AIF RX inputs may be selected as input to the digital mixers or signal processing functions within

the WM8281 digital core. The AIF TX outputs are derived from the respective output mixers.

The sample rate for each digital audio interface AIFn is configured using the respective AIFn_RATE

within the “Digital Core” section.

Note that sample rate conversion is required when routing the AIF paths to any signal chain that is

asynchronous and/or configured for a different sample rate.

AIF MASTER / SLAVE CONTROL

The digital audio interfaces can operate in Master or Slave modes and also in mixed master/slave

configurations. In Master mode, the BCLK and LRCLK signals are generated by the WM8281 when

any of the respective digital audio interface channels is enabled. In Slave mode, these outputs are

disabled by default to allow another device to drive these pins.

Master mode is selected on the AIFnBCLK pin using the AIFn_BCLK_MSTR register bit. In Master

mode, the AIFnBCLK signal is generated by the WM8281 when one or more AIFn channels is

enabled.

When the AIFn_BCLK_FRC bit is set in BCLK master mode, the AIFnBCLK signal is output at all

times, including when none of the AIFn channels is enabled.

The AIFnBCLK signal can be inverted in Master or Slave modes using the AIFn_BCLK_INV register.

Master mode is selected on the AIFnLRCLK pin using the AIFnRX_LRCLK_MSTR register bit. In

Master mode, the AIFnRXLRCLK signal is generated by the WM8281 when one or more AIFn

channels is enabled. (Note that, when GPIOn is configured as AIFnTXLRCLK, then only the AIFn RX

channels will cause AIFnRXLRCLK to be output.)

When the AIFnRX_LRCLK_FRC bit is set in LRCLK master mode, the AIFnRXLRCLK signal is output

at all times, including when none of the AIFn channels is enabled. Note that AIFnRXLRCLK is derived

from AIFnBCLK, and an internal or external AIFnBCLK signal must be present to generate

AIFnRXLRCLK.

The AIFnRXLRCLK signal can be inverted in Master or Slave modes using the AIFnRX_LRCLK_INV

Under default conditions, the AIFn input (RX) and output (TX) paths both use the AIFnRXLRCLK

signal as the frame synchronisation clock. The AIFn output (TX) interface can be configured to use a

separate frame clock, AIFnTXLRCLK, using the AIFnTX_LRCLK_SRC bit.

The AIFnTXLRCLK function, when used, must be selected on the GPIOn pin as described in the

“General Purpose Input / Output” section.

The AIFnTXLRCLK function can operate in Master or Slave mode, and is controlled similarly to the

AIFnRXLRCLK function using the register bits described in Table 31, Table 32 and Table 33 for AIF1,

AIF2 and AIF3 respectively.

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