WM8281ECSSLASHR datasheet(285/392 Pages) CIRRUS

285 / 392 page

WM8281

Rev 4.0

285

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

3:0

FLL2_SYNCCLK

_SRC

0000

FLL2 Synchroniser Clock source

0000 = MCLK1

0001 = MCLK2

0011 = SLIMCLK

0100 = FLL1

0101 = FLL2

1000 = AIF1BCLK

1001 = AIF2BCLK

1010 = AIF3BCLK

1100 = AIF1RXLRCLK

1101 = AIF2RXLRCLK

1110 = AIF3RXLRCLK

All other codes are Reserved

R423

(01A7h)

FLL2

Synchroni

ser 7

5:2

FLL2_SYNC_GAI

N [3:0]

0000

FLL2 Synchroniser Gain

0000 = 1

0001 = 2

0010 = 4

0011 = 8

0100 = 16

0101 = 32

0110 = 64

0111 = 128

1000 to 1111 = 256

FLL2_SYNC_DF

SAT

FLL2 Synchroniser Bandwidth

0 = Wide bandwidth

1 = Narrow bandwidth

Table 107 FLL2 Register Map

FREE-RUNNING FLL MODE

The FLL can generate a clock signal even when no external reference is available. This may be

because the normal input reference has been interrupted, or may be during a standby or start-up

period when no initial reference clock is available.

Free-running FLL mode is enabled using the FLLn_FREERUN register. (Note that FLLn_ENA must

also be enabled in Free-running FLL mode.)

In Free-running FLL mode, the normal feedback mechanism of the FLL is halted, and the FLL

oscillates independently of the external input reference(s).

If the FLL was previously operating normally, (with an input reference clock), then the FLL output

frequency will remain unchanged when Free-running FLL mode is enabled. The FLL output will be

independent of the input reference while operating in free-running mode with FLLn_FREERUN=1.

The main FLL loop will always continue to free-run if the input reference clock is stopped (regardless

of the FLLn_FREERUN setting). If FLLn_FREERUN=0, the FLL will re-lock to the input reference

whenever it is available.

In free-running mode, (with FLLn_FREERUN=1), the FLL integrator value (part of the feedback

mechanism) can be commanded directly using the FLLn_FRC_INTEG_VAL register. The integrator

value in this register is applied to the FLL when a ‘1’ is written to the FLLn_FRC_INTEG_UPD bit.

If the FLL is started up in free-running mode, (ie. it was not previously running), then the default value

of FLLn_FRC_INTEG_VAL will be applied.

The FLL integrator value (part of the feedback mechanism) can be read from the FLLn_INTEG

FLLn_INTEG register is only valid when FLLn_FREERUN=1, and the FLLn_INTEG_VALID bit is set.

The FLL integrator setting does not ensure a specific output frequency for the FLL across all devices

and operating conditions; some level of variation will apply.

The free-running FLL clock may be selected as the SYSCLK source or ASYNCCLK source as shown

Figure 69.

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