WM8281ECSSLASHR datasheet(102/392 Pages) CIRRUS

102 / 392 page

WM8281

102

Rev 4.0

The WM8281 performs automatic checks to confirm that the SYSCLK frequency is high enough to

support the digital mixer paths. If an attempt is made to enable a PWM signal mixer path, and there

are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any

signal paths that are already active will not be affected under these circumstances.)

The Underclocked Error condition can be monitored using the GPIO and/or Interrupt functions. See

“General Purpose Input / Output” and “Interrupts” for further details.

The status bits in Registers R1600 to R3000 indicate the status of each of the digital mixers. If an

Underclocked Error condition occurs, then these bits provide readback of which mixer(s) have been

successfully enabled.

SAMPLE RATE CONTROL

The WM8281 supports multiple signal paths through the digital core. Stereo full-duplex sample rate

conversion is provided to allow digital audio to be routed between interfaces operating at different

sample rates and/or referenced to asynchronous clock domains.

Two independent clock domains are supported, referenced to SYSCLK and ASYNCCLK respectively,

as described in “Clocking and Sample Rates”. Every digital signal path must be synchronised either to

SYSCLK or to ASYNCCLK.

Up to five different sample rates may be in use at any time on the WM8281. Three of these sample

rates must be synchronised to SYSCLK; the remaining two, where required, must be synchronised to

ASYNCCLK.

Sample rate conversion is required when routing any audio path between digital functions that are

asynchronous and/or configured for different sample rates.

The Asynchronous Sample Rate Converter (ASRC) provides two stereo signal paths between the

SYSCLK and ASYNCCLK domains. The ASRC is described later, and is illustrated in Figure 40.

There are three Isochronous Sample Rate Converters (ISRCs). These provide four signal paths each

between sample rates on the SYSCLK domain, or between sample rates on the ASYNCCLK domain.

The ISRCs are described later, and are illustrated in Figure 41.

The sample rate of different blocks within the WM8281 digital core are controlled as illustrated in

Figure 38 and Figure 39 - the *_RATE registers select the applicable sample rate for each respective

group of digital functions.

The *_RATE registers should not be changed if any of the *_SRCn registers associated with the

respective functions is non-zero. The associated *_SRCn registers should be cleared to 00h before

writing new values to the *_RATE registers. A minimum delay of 125µs should be allowed between

clearing the *_SRCn registers and writing to the associated *_RATE registers. See Table 23 for

further details.

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